Searched refs:SplitLHS (Results 1 – 3 of 3) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | ScalarEvolution.cpp | 10909 auto SplitLHS = SplitIntoInitAndPostInc(MDL, LHS); in isKnownViaInduction() local
10911 if (SplitLHS.first == getCouldNotCompute()) in isKnownViaInduction()
10913 assert (SplitLHS.second != getCouldNotCompute() && "Unexpected CNC"); in isKnownViaInduction()
10923 if (!isAvailableAtLoopEntry(SplitLHS.first, MDL) || in isKnownViaInduction()
10929 return isLoopBackedgeGuardedByCond(MDL, Pred, SplitLHS.second, in isKnownViaInduction()
10931 isLoopEntryGuardedByCond(MDL, Pred, SplitLHS.first, SplitRHS.first); in isKnownViaInduction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 12631 static bool isConcatMask(ArrayRef<int> Mask, EVT VT, bool SplitLHS) { in isConcatMask() argument
12644 if (Mask[I] != I + SplitLHS * Offset) in isConcatMask()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 22326 auto SplitLHS = DAG.SplitScalar(DAG.getBitcast(IntVT, MaskBits(LHS)), DL, in LowerVectorAllEqual() local
22331 DAG.getNode(ISD::XOR, DL, MVT::i32, SplitLHS.first, SplitRHS.first); in LowerVectorAllEqual()
22333 DAG.getNode(ISD::XOR, DL, MVT::i32, SplitLHS.second, SplitRHS.second); in LowerVectorAllEqual()
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