Searched refs:SplitF64 (Results 1 – 4 of 4) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfoD.td | 27 def RISCVSplitF64 : RVSDNode<"SplitF64", SDT_RISCVSplitF64>;
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| H A D | RISCVISelDAGToDAG.cpp | 1130 case RISCVISD::SplitF64: { in Select() 1131 if (Subtarget->hasStdExtZdinx() || Opcode != RISCVISD::SplitF64) { in Select()
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| H A D | RISCVISelLowering.cpp | 6917 return DAG.getNode(RISCVISD::SplitF64, DL, {MVT::i32, MVT::i32}, Sign) in lowerFCOPYSIGN() 7961 SDValue Split = DAG.getNode(RISCVISD::SplitF64, DL, in LowerOperation() 14502 SDValue NewReg = DAG.getNode(RISCVISD::SplitF64, DL, in ReplaceNodeResults() 19681 case RISCVISD::SplitF64: { in PerformDAGCombine() 19712 DAG.getNode(RISCVISD::SplitF64, DL, DAG.getVTList(MVT::i32, MVT::i32), in PerformDAGCombine() 22578 SDValue SplitF64 = DAG.getNode( in LowerCall() local 22579 RISCVISD::SplitF64, DL, DAG.getVTList(MVT::i32, MVT::i32), ArgValue); in LowerCall() 22580 SDValue Lo = SplitF64.getValue(0); in LowerCall() 22581 SDValue Hi = SplitF64.getValue(1); in LowerCall() 22866 SDValue SplitF64 = DAG.getNode(RISCVISD::SplitF64, DL, in LowerReturn() local [all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 7384 SDValue SplitF64 = in LowerCall() local 7387 SDValue Lo = SplitF64.getValue(0); in LowerCall() 7388 SDValue Hi = SplitF64.getValue(1); in LowerCall() 7651 SDValue SplitF64 = DAG.getNode(LoongArchISD::SPLIT_PAIR_F64, DL, in LowerReturn() local 7653 SDValue Lo = SplitF64.getValue(0); in LowerReturn() 7654 SDValue Hi = SplitF64.getValue(1); in LowerReturn()
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