Searched refs:SplitF64 (Results 1 – 4 of 4) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.h | 46 SplitF64, enumerator
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| H A D | RISCVInstrInfoD.td | 26 def RISCVSplitF64 : SDNode<"RISCVISD::SplitF64", SDT_RISCVSplitF64>;
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| H A D | RISCVISelLowering.cpp | 12623 SDValue NewReg = DAG.getNode(RISCVISD::SplitF64, DL, in ReplaceNodeResults()
16680 case RISCVISD::SplitF64: { in PerformDAGCombine()
16682 // If the input to SplitF64 is just BuildPairF64 then the operation is in PerformDAGCombine()
16711 DAG.getNode(RISCVISD::SplitF64, DL, DAG.getVTList(MVT::i32, MVT::i32), in PerformDAGCombine()
19976 SDValue SplitF64 = DAG.getNode( in LowerCall()
19977 RISCVISD::SplitF64, DL, DAG.getVTList(MVT::i32, MVT::i32), ArgValue); in LowerCall()
19978 SDValue Lo = SplitF64.getValue(0); in LowerCall()
19979 SDValue Hi = SplitF64.getValue(1); in LowerCall()
20249 SDValue SplitF64 = DAG.getNode(RISCVISD::SplitF64, D in LowerReturn()
19973 SDValue SplitF64 = DAG.getNode( LowerCall() local
20246 SDValue SplitF64 = DAG.getNode(RISCVISD::SplitF64, DL, LowerReturn() local
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| H A D | RISCVISelDAGToDAG.cpp | 1032 case RISCVISD::SplitF64: { in Select()
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