| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.h | 139 bool selectVSplat(SDValue N, SDValue &SplatVal);
140 bool selectVSplatSimm5(SDValue N, SDValue &SplatVal);
141 bool selectVSplatUimm(SDValue N, unsigned Bits, SDValue &SplatVal);
145 bool selectVSplatSimm5Plus1(SDValue N, SDValue &SplatVal);
146 bool selectVSplatSimm5Plus1NoDec(SDValue N, SDValue &SplatVal);
147 bool selectVSplatSimm5Plus1NonZero(SDValue N, SDValue &SplatVal);
148 bool selectVSplatImm64Neg(SDValue N, SDValue &SplatVal);
151 bool selectLow8BitsVSplat(SDValue N, SDValue &SplatVal);
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| H A D | RISCVISelDAGToDAG.cpp | 3841 bool RISCVDAGToDAGISel::selectVSplat(SDValue N, SDValue &SplatVal) { in selectVSplat() argument
3846 SplatVal = Splat.getOperand(1); in selectVSplat()
3850 static bool selectVSplatImmHelper(SDValue N, SDValue &SplatVal, in selectVSplatImmHelper() argument
3880 SplatVal = in selectVSplatImmHelper()
3885 bool RISCVDAGToDAGISel::selectVSplatSimm5(SDValue N, SDValue &SplatVal) { in selectVSplatSimm5() argument
3886 return selectVSplatImmHelper(N, SplatVal, *CurDAG, *Subtarget, in selectVSplatSimm5()
3890 bool RISCVDAGToDAGISel::selectVSplatSimm5Plus1(SDValue N, SDValue &SplatVal) { in selectVSplatSimm5Plus1() argument
3892 N, SplatVal, *CurDAG, *Subtarget, in selectVSplatSimm5Plus1()
3897 bool RISCVDAGToDAGISel::selectVSplatSimm5Plus1NoDec(SDValue N, SDValue &SplatVal) { in selectVSplatSimm5Plus1NoDec() argument
3899 N, SplatVal, *CurDAG, *Subtarget, in selectVSplatSimm5Plus1NoDec()
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| H A D | RISCVISelLowering.cpp | 3696 static SDValue matchSplatAsGather(SDValue SplatVal, MVT VT, const SDLoc &DL, in matchSplatAsGather() argument
3699 if (SplatVal.getOpcode() != ISD::EXTRACT_VECTOR_ELT) in matchSplatAsGather()
3701 SDValue Src = SplatVal.getOperand(0); in matchSplatAsGather()
3710 SDValue Idx = SplatVal.getOperand(1); in matchSplatAsGather()
9514 SDValue SplatVal = Op.getOperand(0); in lowerVectorMaskSplat() local
9525 SplatVal = DAG.getNode(ISD::AND, DL, SplatVal.getValueType(), SplatVal, in lowerVectorMaskSplat()
9526 DAG.getConstant(1, DL, SplatVal.getValueType())); in lowerVectorMaskSplat()
9527 SDValue LHS = DAG.getSplatVector(InterVT, DL, SplatVal); in lowerVectorMaskSplat()
19389 APInt &SplatVal) { in combineTruncToVnclip() argument
19406 if (ISD::isConstantSplatVector(Op.getNode(), SplatVal)) in combineTruncToVnclip()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelDAGToDAG.cpp | 392 bool LoongArchDAGToDAGISel::selectVSplatImm(SDValue N, SDValue &SplatVal) { in selectVSplatImm() argument
402 SplatVal = CurDAG->getSignedTargetConstant( in selectVSplatImm()
407 SplatVal = CurDAG->getTargetConstant(ImmValue.getZExtValue(), SDLoc(N), in selectVSplatImm()
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| H A D | LoongArchISelDAGToDAG.h | 63 bool selectVSplatImm(SDValue N, SDValue &SplatVal);
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| /freebsd/contrib/llvm-project/llvm/lib/IR/ |
| H A D | Constants.cpp | 118 if (const auto *SplatVal = getSplatValue()) in isAllOnesValue() local
119 return SplatVal->isAllOnesValue(); in isAllOnesValue()
135 if (const auto *SplatVal = getSplatValue()) in isOneValue() local
136 return SplatVal->isOneValue(); in isOneValue()
162 if (const auto *SplatVal = getSplatValue()) in isNotOneValue() local
163 return SplatVal->isNotOneValue(); in isNotOneValue()
180 if (const auto *SplatVal = getSplatValue()) in isMinSignedValue() local
181 return SplatVal->isMinSignedValue(); in isMinSignedValue()
207 if (const auto *SplatVal = getSplatValue()) in isNotMinSignedValue() local
208 return SplatVal->isNotMinSignedValue(); in isNotMinSignedValue()
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| H A D | AsmWriter.cpp | 1763 if (auto *SplatVal = CV->getSplatValue()) { in WriteConstantInternal() local
1764 if (isa<ConstantInt>(SplatVal) || isa<ConstantFP>(SplatVal)) { in WriteConstantInternal()
1768 WriteAsOperandInternal(Out, SplatVal, WriterCtx); in WriteConstantInternal()
1815 if (auto *SplatVal = CE->getSplatValue()) { in WriteConstantInternal() local
1816 if (isa<ConstantInt>(SplatVal) || isa<ConstantFP>(SplatVal)) { in WriteConstantInternal()
1818 WriterCtx.TypePrinter->print(SplatVal->getType(), Out); in WriteConstantInternal()
1820 WriteAsOperandInternal(Out, SplatVal, WriterCtx); in WriteConstantInternal()
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| H A D | ConstantFold.cpp | 397 if (Constant *SplatVal = Val->getSplatValue()) in ConstantFoldExtractElementInstruction() local
398 return SplatVal; in ConstantFoldExtractElementInstruction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIFoldOperands.cpp | 234 int64_t SplatVal,
1038 MachineInstr *UseMI, unsigned UseOpIdx, int64_t SplatVal, in tryFoldRegSeqSplat() argument
1057 if (SplatVal != 0 && SplatVal != -1) { in tryFoldRegSeqSplat()
1078 MachineOperand TmpOp = MachineOperand::CreateImm(SplatVal); in tryFoldRegSeqSplat()
1160 int64_t SplatVal; in foldOperand() local
1162 std::tie(SplatVal, SplatRC) = isRegSeqSplat(*UseMI); in foldOperand()
1172 if (tryFoldRegSeqSplat(RSUseMI, OpNo, SplatVal, SplatRC)) { in foldOperand()
1173 FoldableDef SplatDef(SplatVal, SplatRC); in foldOperand()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVLegalizerInfo.cpp | 1016 Register SplatVal = MI.getOperand(1).getReg(); in legalizeSplatVector() local
1025 buildSplatSplitS64WithVL(Dst, MIB.buildUndef(VecTy), SplatVal, VL, MIB, in legalizeSplatVector()
1032 MachineInstr &SplatValMI = *MRI.getVRegDef(SplatVal); in legalizeSplatVector()
1050 auto ZExtSplatVal = MIB.buildZExt(InterEltTy, SplatVal); in legalizeSplatVector()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineVectorOps.cpp | 1309 Value *SplatVal = InsElt.getOperand(1); in foldInsSequenceIntoSplat() local
1318 if (!Idx || CurrIE->getOperand(1) != SplatVal) in foldInsSequenceIntoSplat()
1351 FirstIE = InsertElementInst::Create(PoisonVec, SplatVal, Zero, "", in foldInsSequenceIntoSplat()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 11559 SDValue SplatVal = DAG.getSExtOrTrunc(CCVal, DL, SplatValVT); in LowerSELECT() local
11560 SDValue SplatPred = DAG.getNode(ISD::SPLAT_VECTOR, DL, PredVT, SplatVal); in LowerSELECT()
14180 SDValue SplatVal = DAG.getAnyExtOrTrunc(Op.getOperand(0), DL, MVT::i64); in LowerSPLAT_VECTOR() local
14181 SplatVal = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i64, SplatVal, in LowerSPLAT_VECTOR()
14189 Zero, SplatVal), in LowerSPLAT_VECTOR()
14191 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, ID, Zero, SplatVal); in LowerSPLAT_VECTOR()
15555 static bool isPow2Splat(SDValue Op, uint64_t &SplatVal, bool &Negated) { in isPow2Splat() argument
15562 !isAllConstantBuildVector(Op, SplatVal)) in isPow2Splat()
15569 SplatVal = Op->getConstantOperandVal(0); in isPow2Splat()
15571 SplatVal = (int32_t)SplatVal; in isPow2Splat()
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| H A D | AArch64TargetTransformInfo.cpp | 1926 if (auto *SplatVal = getSplatValue(Vec)) in instCombineSVELast() local
1927 return IC.replaceInstUsesWith(II, SplatVal); in instCombineSVELast()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.h | 1035 bool isConstantSplat(SDValue Op, APInt &SplatVal,
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| H A D | X86ISelDAGToDAG.cpp | 1021 APInt SplatVal; in PreprocessISelDAG() local
1022 if (X86::isConstantSplat(N->getOperand(1), SplatVal) && in PreprocessISelDAG()
1023 SplatVal.isOne()) { in PreprocessISelDAG()
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| H A D | X86ISelLowering.cpp | 5323 bool isConstantSplat(SDValue Op, APInt &SplatVal, bool AllowPartialUndefs) { in isConstantSplat() argument
5340 SplatVal = EltBits[SplatIndex]; in isConstantSplat()
33936 APInt SplatVal; in ReplaceNodeResults() local
33937 if (ISD::isConstantSplatVector(N->getOperand(1).getNode(), SplatVal)) { in ReplaceNodeResults()
33943 SDValue N1 = DAG.getConstant(SplatVal, dl, ResVT); in ReplaceNodeResults()
51169 APInt SplatVal; in combineAndMaskToShift() local
51170 if (!X86::isConstantSplat(Op1, SplatVal, false) || !SplatVal.isMask()) in combineAndMaskToShift()
51184 unsigned ShiftVal = SplatVal.countr_one(); in combineAndMaskToShift()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAG.cpp | 151 bool ISD::isConstantSplatVector(const SDNode *N, APInt &SplatVal) { in isConstantSplatVector() argument
156 SplatVal = OptAPInt->trunc(EltSize); in isConstantSplatVector()
174 return BV->isConstantSplat(SplatVal, SplatUndef, SplatBitSize, HasUndefs, in isConstantSplatVector()
188 APInt SplatVal; in isConstantSplatVectorAllOnes() local
189 return isConstantSplatVector(N, SplatVal) && SplatVal.isAllOnes(); in isConstantSplatVectorAllOnes()
234 APInt SplatVal; in isConstantSplatVectorAllZeros() local
235 return isConstantSplatVector(N, SplatVal) && SplatVal.isZero(); in isConstantSplatVectorAllZeros()
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| H A D | DAGCombiner.cpp | 12458 if (SDValue SplatVal = DAG.getSplatValue(Index); in refineUniformBase() local
12459 SplatVal && !isNullConstant(SplatVal) && in refineUniformBase()
12460 SplatVal.getValueType() == VT) { in refineUniformBase()
12461 BasePtr = DAG.getNode(ISD::ADD, DL, VT, BasePtr, SplatVal); in refineUniformBase()
12469 if (SDValue SplatVal = DAG.getSplatValue(Index.getOperand(0)); in refineUniformBase() local
12470 SplatVal && SplatVal.getValueType() == VT) { in refineUniformBase()
12471 BasePtr = DAG.getNode(ISD::ADD, DL, VT, BasePtr, SplatVal); in refineUniformBase()
12475 if (SDValue SplatVal = DAG.getSplatValue(Index.getOperand(1)); in refineUniformBase() local
12476 SplatVal && SplatVal.getValueType() == VT) { in refineUniformBase()
12477 BasePtr = DAG.getNode(ISD::ADD, DL, VT, BasePtr, SplatVal); in refineUniformBase()
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| H A D | LegalizeDAG.cpp | 2116 SDValue SplatVal = Node->getOperand(0); in ExpandSPLAT_VECTOR() local
2118 return DAG.getSplatBuildVector(VT, DL, SplatVal); in ExpandSPLAT_VECTOR()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | IRTranslator.cpp | 3323 auto SplatVal = MIRBuilder.buildExtractVectorElementConstant( in translateShuffleVector() local
3325 MIRBuilder.buildSplatVector(getOrCreateVReg(U), SplatVal); in translateShuffleVector()
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| H A D | LegalizerHelper.cpp | 9698 APInt SplatVal = APInt::getSplat(NumBits, Scalar); in getMemsetValue() local
9699 return MIB.buildConstant(Ty, SplatVal).getReg(0); in getMemsetValue()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 3000 auto IsZeroSplat = [](SDValue SplatVal) { in performVectorTruncZeroCombine() argument
3001 auto *Splat = dyn_cast<BuildVectorSDNode>(SplatVal.getNode()); in performVectorTruncZeroCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 8255 SDValue SplatVal = Op1->getOperand(0); in combineSTORE() local
8256 if (auto *C = dyn_cast<ConstantSDNode>(SplatVal)) in combineSTORE()
8257 FindReplicatedImm(C, SplatVal.getValueType().getStoreSize()); in combineSTORE()
8259 FindReplicatedReg(SplatVal); in combineSTORE()
8272 SDValue SplatVal = DAG.getSplatVector(SplatVT, SDLoc(SN), Word); in combineSTORE() local
8273 return DAG.getStore(SN->getChain(), SDLoc(SN), SplatVal, in combineSTORE()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 10349 unsigned SplatVal = APSplatValue.getZExtValue(); in lowerToXXSPLTI32DX() local
10351 SplatVal |= (SplatVal << SplatBitSize); in lowerToXXSPLTI32DX()
10355 Index, DAG.getTargetConstant(SplatVal, DL, MVT::i32)); in lowerToXXSPLTI32DX()
16557 SDValue SplatVal = in combineVectorShuffle() local
16559 TheSplat = DAG.getSplatBuildVector(TheSplat.getValueType(), dl, SplatVal); in combineVectorShuffle()
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