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Searched refs:Spills (Results 1 – 7 of 7) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DLiveInterval.cpp1104 // - When LastStart is invalid, Spills is empty and the iterators are invalid.
1112 // 3. Spills.
1117 // - Segments in Spills precede and can't coalesce with segments in area 2.
1118 // - No coalescing is possible between segments in Spills and segments in area
1121 // The segments in Spills are not ordered with respect to the segments in area
1124 // When they exist, Spills.back().start <= LastStart,
1142 OS << "\n Spills:"; in print()
1143 for (unsigned I = 0, E = Spills.size(); I != E; ++I) in print()
1144 OS << ' ' << Spills[I]; in print()
1183 assert(Spills in add()
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H A DRegAllocGreedy.h414 unsigned Spills = 0; member
424 return !(Reloads || FoldedReloads || Spills || FoldedSpills || in isEmpty()
432 Spills += other.Spills; in add()
H A DInlineSpiller.cpp115 SmallPtrSet<MachineInstr *, 16> &Spills,
120 MachineBasicBlock *Root, SmallPtrSet<MachineInstr *, 16> &Spills,
127 SmallPtrSet<MachineInstr *, 16> &Spills,
1376 SmallPtrSet<MachineInstr *, 16> &Spills, in rmRedundantSpills() argument
1382 for (auto *const CurrentSpill : Spills) { in rmRedundantSpills()
1398 Spills.erase(SpillToRm); in rmRedundantSpills()
1408 MachineBasicBlock *Root, SmallPtrSet<MachineInstr *, 16> &Spills, in getVisitOrders() argument
1431 for (auto *const Spill : Spills) { in getVisitOrders()
1493 SmallPtrSet<MachineInstr *, 16> &Spills, in runHoistSpills() argument
1507 rmRedundantSpills(Spills, SpillsToRm, SpillBBToSpill); in runHoistSpills()
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H A DRegAllocGreedy.cpp2520 if (Spills) { in report()
2521 R << NV("NumSpills", Spills) << " spills "; in report()
2592 ++Stats.Spills; in computeStats()
2633 Stats.SpillsCost = RelFreq * Stats.Spills; in computeStats()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Coroutines/
H A DCoroFrame.cpp471 SpillInfo Spills; member
478 for (const auto &P : Spills) in getAllDefs()
553 static void dumpSpills(StringRef Title, const SpillInfo &Spills) { in dumpSpills() argument
555 for (const auto &E : Spills) { in dumpSpills()
752 for (auto &S : Spills) in updateLayoutIndex()
1357 for (auto &S : FrameData.Spills) { in buildFrameType()
1813 for (auto const &E : FrameData.Spills) { in insertSpills()
3042 SpillInfo Spills; in doRematerializations() local
3052 Spills[&I].push_back(cast<Instruction>(U)); in doRematerializations()
3071 for (auto &E : Spills) { in doRematerializations()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DLiveInterval.h946 SmallVector<LiveRange::Segment, 16> Spills; variable
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstructions.td856 // that switch the VGPR indexing mode. Spills to accvgprs could be effected by