Searched refs:SpillToPhysVGPRLane (Results 1 – 4 of 4) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.h | 185 bool SpillToPhysVGPRLane = false) const; 190 bool SpillToPhysVGPRLane = false) const; 203 bool SpillToPhysVGPRLane = false) const;
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| H A D | SIMachineFunctionInfo.cpp | 432 MachineFunction &MF, int FI, bool SpillToPhysVGPRLane, in allocateSGPRSpillToVGPRLane() argument 435 SpillToPhysVGPRLane ? SGPRSpillsToPhysicalVGPRLanes[FI] in allocateSGPRSpillToVGPRLane() 456 unsigned &NumSpillLanes = SpillToPhysVGPRLane ? NumPhysicalVGPRSpillLanes in allocateSGPRSpillToVGPRLane() 462 bool Allocated = SpillToPhysVGPRLane in allocateSGPRSpillToVGPRLane()
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| H A D | SIRegisterInfo.cpp | 2032 bool SpillToPhysVGPRLane) const { in spillSGPR() 2039 SpillToPhysVGPRLane ? SB.MFI.getSGPRSpillToPhysicalVGPRLanes(Index) in spillSGPR() 2163 bool SpillToPhysVGPRLane) const { in restoreSGPR() 2167 SpillToPhysVGPRLane ? SB.MFI.getSGPRSpillToPhysicalVGPRLanes(Index) in restoreSGPR() 2317 SlotIndexes *Indexes, LiveIntervals *LIS, bool SpillToPhysVGPRLane) const { in eliminateSGPRToVGPRSpillFrameIndex() 2333 return spillSGPR(MI, FI, RS, Indexes, LIS, true, SpillToPhysVGPRLane); in eliminateSGPRToVGPRSpillFrameIndex() 2348 return restoreSGPR(MI, FI, RS, Indexes, LIS, true, SpillToPhysVGPRLane); in eliminateSGPRToVGPRSpillFrameIndex()
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| H A D | SIMachineFunctionInfo.h | 807 bool SpillToPhysVGPRLane = false,
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