| /freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/ |
| H A D | InfoByHwMode.cpp | 122 SpillSize = R->getValueAsInt("SpillSize"); in RegSizeInfo()
127 return std::tie(RegSize, SpillSize, SpillAlignment) < in operator <()
128 std::tie(I.RegSize, I.SpillSize, I.SpillAlignment); in operator <()
133 I.SpillAlignment % SpillAlignment == 0 && SpillSize <= I.SpillSize; in isSubClassOf()
137 OS << "[R=" << RegSize << ",S=" << SpillSize << ",A=" << SpillAlignment in writeToStream()
171 return std::tie(A0.SpillSize, A0.SpillAlignment) > in hasStricterSpillThan()
172 std::tie(B0.SpillSize, B0.SpillAlignment); in hasStricterSpillThan()
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| H A D | InfoByHwMode.h | 184 unsigned SpillSize; member
191 return std::tie(RegSize, SpillSize, SpillAlignment) ==
192 std::tie(I.RegSize, I.SpillSize, I.SpillAlignment);
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| H A D | CodeGenRegisters.cpp | 740 RI.RegSize = RI.SpillSize = in CodeGenRegisterClass()
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | RegisterBankEmitter.cpp | 90 else if (RCsWithLargestRegSize[M]->RSI.get(M).SpillSize < in addRegisterClass()
91 RC->RSI.get(M).SpillSize) in addRegisterClass()
279 unsigned Size = RC.RSI.get(M).SpillSize; in emitBaseClassImplementation()
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| H A D | RegisterInfoEmitter.cpp | 1325 OS << " { " << RI.RegSize << ", " << RI.SpillSize << ", " in runTargetDesc()
1881 OS << ' ' << getModeName(M) << ':' << RC.RSI.get(M).SpillSize; in debugDump()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | PrologEpilogInserter.cpp | 316 int64_t SpillSize = 0; in run() local
320 SpillSize += MFI.getObjectSize(Idx); in run()
324 static_cast<float>(SpillSize) / static_cast<float>(StackSize); in run()
327 SpillSize, StackSize, StackSize - SpillSize, SpillPct, in run()
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| H A D | LiveDebugVariables.cpp | 1586 unsigned SpillSize; in rewriteLocations() local
1589 bool Success = TII.getStackSlotRange(TRC, Loc.getSubReg(), SpillSize, in rewriteLocations()
1901 unsigned SpillSize, SpillOffset; in emitDebugValues() local
1911 TII->getStackSlotRange(TRC, SubReg, SpillSize, SpillOffset, *MF); in emitDebugValues()
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| H A D | TargetInstrInfo.cpp | 617 unsigned SpillSize; in foldPatchpoint() local
623 TII.getStackSlotRange(RC, MO.getSubReg(), SpillSize, SpillOffset, MF); in foldPatchpoint()
627 MIB.addImm(SpillSize); in foldPatchpoint()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 242 unsigned RegSize, SpillSize, SpillAlignment; member
303 return getRegClassInfo(RC).SpillSize / 8; in getSpillSize()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | StatepointLowering.cpp | 112 unsigned SpillSize = ValueType.getStoreSize(); in allocateStackSlot() local
113 assert((SpillSize * 8) == in allocateStackSlot()
131 if (MFI.getObjectSize(FI) == SpillSize) { in allocateStackSlot()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 1743 unsigned SpillSize = TRI->getSpillSize(*RC); in storeRegToStackSlot() local
1754 const MCInstrDesc &OpDesc = get(getSGPRSpillSaveOpcode(SpillSize)); in storeRegToStackSlot()
1758 if (SrcReg.isVirtual() && SpillSize == 4) { in storeRegToStackSlot()
1774 SpillSize, RI, *MFI); in storeRegToStackSlot()
1967 unsigned SpillSize = TRI->getSpillSize(*RC); in loadRegFromStackSlot() local
1984 const MCInstrDesc &OpDesc = get(getSGPRSpillRestoreOpcode(SpillSize)); in loadRegFromStackSlot()
1985 if (DestReg.isVirtual() && SpillSize == 4) { in loadRegFromStackSlot()
2001 SpillSize, RI, *MFI); in loadRegFromStackSlot()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCFrameLowering.cpp | 2061 const uint64_t SpillSize = 4; // Condition register is always 4 bytes. in determineCalleeSaves() local
2065 MFI.CreateFixedObject(SpillSize, SpillOffset, in determineCalleeSaves()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FrameLowering.cpp | 4058 auto SpillSize = TRI->getSpillSize(*RC); in determineCalleeSaves() local
4061 SVECSStackSize += SpillSize; in determineCalleeSaves()
4063 CSStackSize += SpillSize; in determineCalleeSaves()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 8411 unsigned SpillSize = STI.getRegisterInfo()->getSpillSize(*RC); in getBroadcastOpcode() local
8412 assert((SpillSize == 64 || STI.hasVLX()) && in getBroadcastOpcode()
8417 switch (SpillSize) { \ in getBroadcastOpcode()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | Target.td | 80 int SpillSize = SS; // Spill slot size in bits.
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