| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RegAllocBasic.cpp | 227 for (const LiveInterval *Spill : Intfs) { in spillInterferences() local
229 if (!VRM->hasPhys(Spill->reg())) in spillInterferences()
234 Matrix->unassign(*Spill); in spillInterferences()
237 LiveRangeEdit LRE(Spill, SplitVRegs, *MF, *LIS, VRM, this, &DeadRemats); in spillInterferences()
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| H A D | InlineSpiller.cpp | 143 void addToMergeableSpills(MachineInstr &Spill, int StackSlot,
145 bool rmFromMergeableSpills(MachineInstr &Spill, int StackSlot);
1127 MachineBasicBlock::iterator Spill = std::next(MI); in insertSpill() local
1128 LIS.InsertMachineInstrRangeInMaps(Spill, MIS.end()); in insertSpill()
1129 for (const MachineInstr &MI : make_range(Spill, MIS.end())) in insertSpill()
1133 dumpMachineInstrRangeWithSlotIndex(Spill, MIS.end(), LIS, "spill")); in insertSpill()
1138 if (IsRealSpill && std::distance(Spill, MIS.end()) <= 1) in insertSpill()
1139 HSpiller.addToMergeableSpills(*Spill, StackSlot, Original); in insertSpill()
1315 void HoistSpillHelper::addToMergeableSpills(MachineInstr &Spill, int StackSlot, in addToMergeableSpills() argument
1326 SlotIndex Idx = LIS.getInstructionIndex(Spill); in addToMergeableSpills()
[all …]
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| H A D | StackFrameLayoutAnalysisPass.cpp | 53 Spill, // a Spill slot enumerator
76 SlotTy = SlotType::Spill; in SlotData()
137 case SlotType::Spill: in getTypeString()
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| H A D | MachineCopyPropagation.cpp | 1212 for (const MachineInstr *Spill : drop_begin(SC)) in EliminateSpillageCopies() local
1213 if (CopySourceInvalid.count(Spill)) in EliminateSpillageCopies()
1278 auto IsSpillReloadPair = [&, this](const MachineInstr &Spill, in EliminateSpillageCopies()
1280 if (!IsFoldableCopy(Spill) || !IsFoldableCopy(Reload)) in EliminateSpillageCopies()
1283 isCopyInstr(Spill, *TII, UseCopyInstr); in EliminateSpillageCopies()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIMachineFunctionInfo.h | 625 [&Reg](const auto &Spill) { return Spill.first == Reg; });
632 [&Reg](const auto &Spill) { return Spill.first == Reg; });
662 [&Reg](const auto &Spill) { return Spill.first == Reg; });
950 void setHasSpilledSGPRs(bool Spill = true) {
951 HasSpilledSGPRs = Spill;
958 void setHasSpilledVGPRs(bool Spill = true) {
959 HasSpilledVGPRs = Spill;
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| H A D | SIFrameLowering.cpp | 106 LLVM_DEBUG(auto Spill = MFI->getSGPRSpillToPhysicalVGPRLanes(FI).front(); in getVGPRSpillLaneOrTempRegister()
108 << printReg(Spill.VGPR, TRI) << ':' << Spill.Lane in getVGPRSpillLaneOrTempRegister()
270 ArrayRef<SIRegisterInfo::SpilledReg> Spill = in saveToVGPRLane() local
272 assert(Spill.size() == NumSubRegs); in saveToVGPRLane()
279 Spill[I].VGPR) in saveToVGPRLane()
281 .addImm(Spill[I].Lane) in saveToVGPRLane()
282 .addReg(Spill[I].VGPR, RegState::Undef); in saveToVGPRLane()
316 ArrayRef<SIRegisterInfo::SpilledReg> Spill = in restoreFromVGPRLane() local
318 assert(Spill.size() == NumSubRegs); in restoreFromVGPRLane()
325 .addReg(Spill[I].VGPR) in restoreFromVGPRLane()
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| H A D | SIMachineFunctionInfo.cpp | 455 auto &Spill = VGPRToAGPRSpills[FI]; in allocateVGPRSpillToAGPR() local
458 if (!Spill.Lanes.empty()) in allocateVGPRSpillToAGPR()
459 return Spill.FullyAllocated; in allocateVGPRSpillToAGPR()
463 Spill.Lanes.resize(NumLanes, AMDGPU::NoRegister); in allocateVGPRSpillToAGPR()
471 Spill.FullyAllocated = true; in allocateVGPRSpillToAGPR()
499 Spill.FullyAllocated = false; in allocateVGPRSpillToAGPR()
506 Spill.Lanes[I] = *NextSpillReg++; in allocateVGPRSpillToAGPR()
509 return Spill.FullyAllocated; in allocateVGPRSpillToAGPR()
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| H A D | SIInstrFormats.td | 50 field bit Spill = 0;
189 let TSFlags{26} = Spill;
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| H A D | SIRegisterInfo.cpp | 1786 SpilledReg Spill = VGPRSpills[i]; in spillSGPR() local
1796 SB.TII.get(AMDGPU::SI_SPILL_S32_TO_VGPR), Spill.VGPR) in spillSGPR()
1798 .addImm(Spill.Lane) in spillSGPR()
1799 .addReg(Spill.VGPR); in spillSGPR()
1903 SpilledReg Spill = VGPRSpills[i]; in restoreSGPR() local
1906 .addReg(Spill.VGPR) in restoreSGPR()
1907 .addImm(Spill.Lane); in restoreSGPR()
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| H A D | SIDefines.h | 92 Spill = 1 << 26, enumerator
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| H A D | SIInstrInfo.h | 741 return get(Opcode).TSFlags & SIInstrFlags::Spill; in isSpill()
745 return MI.getDesc().TSFlags & SIInstrFlags::Spill; in isSpill()
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| H A D | SIInstructions.td | 901 let UseNamedOperandTable = 1, Spill = 1, SALU = 1, Uses = [EXEC] in {
937 let Spill = 1, VALU = 1, isConvergent = 1 in {
957 } // End Spill = 1, VALU = 1, isConvergent = 1
963 let UseNamedOperandTable = 1, Spill = 1, VALU = 1,
989 } // End UseNamedOperandTable = 1, Spill = 1, VALU = 1, SchedRW = [WriteVMEM]
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| H A D | SIInstrInfo.cpp | 5554 !(TID.TSFlags & SIInstrFlags::Spill)) || in adjustAllocatableRegClass()
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| /freebsd/contrib/llvm-project/compiler-rt/lib/xray/ |
| H A D | xray_trampoline_powerpc64_asm.S | 8 # Spill r3-r10, f1-f13, and vsr34-vsr45, which are parameter registers.
149 # Spill r3-r4, f1-f8, and vsr34-vsr41, which are return registers.
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| /freebsd/contrib/llvm-project/lld/ELF/ |
| H A D | InputSection.h | 64 enum Kind { Regular, Synthetic, Spill, EHFrame, Merge, Output }; enumerator
408 s->kind() == SectionBase::Spill; in classof()
467 return sec->kind() == InputSectionBase::Spill; in classof()
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| H A D | InputSection.cpp | 199 case Spill: in getOffset()
351 source.name, SectionBase::Spill),
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| H A D | Options.td | 202 …HelpText<"Spill input sections to later matching output sections to avoid memory region overflow">;
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/LiveDebugValues/ |
| H A D | InstrRefBasedImpl.h | 808 unsigned getLocID(SpillLocationNo Spill, unsigned SpillSubReg) {
811 return getLocID(Spill, {Size, Offs});
817 unsigned getLocID(SpillLocationNo Spill, StackSlotPos Idx) {
818 unsigned SlotNo = Spill.id() - 1;
828 unsigned getSpillIDWithIdx(SpillLocationNo Spill, unsigned Idx) {
829 unsigned SlotNo = Spill.id() - 1;
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| H A D | InstrRefBasedImpl.cpp | 1264 const SpillLoc &Spill = SpillLocs[SpillID.id()]; in emitLoc() local
1265 unsigned Base = Spill.SpillBase; in emitLoc()
1295 TRI.getOffsetOpcodes(Spill.SpillOffset, OffsetOps); in emitLoc()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | FunctionLoweringInfo.h | 105 Spill, enumerator
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | StatepointLowering.cpp | 184 if (Record.type != RecordType::Spill) in findPreviousSpillSlot()
926 Record.type = RecordType::Spill; in LowerAsSTATEPOINT()
1255 if (Record.type == RecordType::Spill) { in visitGCRelocate()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | Target.td | 75 int SpillSize = SS; // Spill slot size in bits.
76 int SpillAlignment = SA; // Spill slot alignment in bits.
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SMEInstrInfo.td | 152 // Spill + fill
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| /freebsd/contrib/llvm-project/clang/include/clang/Basic/ |
| H A D | arm_sme.td | 705 // Spill and fill of ZT0
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| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | IntrinsicsAArch64.td | 2839 // Spill + fill
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