| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RegAllocBasic.cpp | 230 for (const LiveInterval *Spill : Intfs) { in spillInterferences() local
232 if (!VRM->hasPhys(Spill->reg())) in spillInterferences()
237 Matrix->unassign(*Spill); in spillInterferences()
240 LiveRangeEdit LRE(Spill, SplitVRegs, *MF, *LIS, VRM, this, &DeadRemats); in spillInterferences()
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| H A D | InlineSpiller.cpp | 138 void addToMergeableSpills(MachineInstr &Spill, int StackSlot,
140 bool rmFromMergeableSpills(MachineInstr &Spill, int StackSlot);
1146 MachineBasicBlock::iterator Spill = std::next(MI); in insertSpill() local
1147 LIS.InsertMachineInstrRangeInMaps(Spill, MIS.end()); in insertSpill()
1148 for (const MachineInstr &MI : make_range(Spill, MIS.end())) in insertSpill()
1152 dumpMachineInstrRangeWithSlotIndex(Spill, MIS.end(), LIS, "spill")); in insertSpill()
1157 if (IsRealSpill && std::distance(Spill, MIS.end()) <= 1) in insertSpill()
1158 HSpiller.addToMergeableSpills(*Spill, StackSlot, Original); in insertSpill()
1339 void HoistSpillHelper::addToMergeableSpills(MachineInstr &Spill, int StackSlot, in addToMergeableSpills() argument
1353 SlotIndex Idx = LIS.getInstructionIndex(Spill); in addToMergeableSpills()
[all …]
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| H A D | StackFrameLayoutAnalysisPass.cpp | 54 Spill, // a Spill slot enumerator
77 SlotTy = SlotType::Spill; in SlotData()
126 case SlotType::Spill: in getTypeString()
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| H A D | MachineCopyPropagation.cpp | 1331 for (const MachineInstr *Spill : drop_begin(SC)) in EliminateSpillageCopies() local
1332 if (CopySourceInvalid.count(Spill)) in EliminateSpillageCopies()
1397 auto IsSpillReloadPair = [&, this](const MachineInstr &Spill, in EliminateSpillageCopies()
1399 if (!IsFoldableCopy(Spill) || !IsFoldableCopy(Reload)) in EliminateSpillageCopies()
1402 isCopyInstr(Spill, *TII, UseCopyInstr); in EliminateSpillageCopies()
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| H A D | LiveInterval.cpp | 1165 for (const LiveRange::Segment &Spill : Spills) in print() local
1166 OS << ' ' << Spill; in print()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIMachineFunctionInfo.h | 698 const auto *I = find_if(PrologEpilogSGPRSpills, [&Reg](const auto &Spill) {
699 return Spill.first == Reg;
706 const auto *I = find_if(PrologEpilogSGPRSpills, [&Reg](const auto &Spill) {
707 return Spill.first == Reg;
737 const auto *I = find_if(PrologEpilogSGPRSpills, [&Reg](const auto &Spill) {
738 return Spill.first == Reg;
1041 void setHasSpilledSGPRs(bool Spill = true) {
1042 HasSpilledSGPRs = Spill;
1049 void setHasSpilledVGPRs(bool Spill = true) {
1050 HasSpilledVGPRs = Spill;
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| H A D | SILowerSGPRSpills.cpp | 311 for (auto &Spill : VGPRSpills) { in updateLaneVGPRDomInstr() local
312 if (PrevLaneVGPR == Spill.VGPR) in updateLaneVGPRDomInstr()
315 PrevLaneVGPR = Spill.VGPR; in updateLaneVGPRDomInstr()
316 auto I = LaneVGPRDomInstr.find(Spill.VGPR); in updateLaneVGPRDomInstr()
317 if (Spill.Lane == 0 && I == LaneVGPRDomInstr.end()) { in updateLaneVGPRDomInstr()
319 LaneVGPRDomInstr[Spill.VGPR] = InsertPt; in updateLaneVGPRDomInstr()
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| H A D | SIFrameLowering.cpp | 106 LLVM_DEBUG(auto Spill = MFI->getSGPRSpillToPhysicalVGPRLanes(FI).front(); in getVGPRSpillLaneOrTempRegister()
108 << printReg(Spill.VGPR, TRI) << ':' << Spill.Lane in getVGPRSpillLaneOrTempRegister()
270 ArrayRef<SIRegisterInfo::SpilledReg> Spill = in saveToVGPRLane() local
272 assert(Spill.size() == NumSubRegs); in saveToVGPRLane()
279 Spill[I].VGPR) in saveToVGPRLane()
281 .addImm(Spill[I].Lane) in saveToVGPRLane()
282 .addReg(Spill[I].VGPR, RegState::Undef); in saveToVGPRLane()
317 ArrayRef<SIRegisterInfo::SpilledReg> Spill = in restoreFromVGPRLane() local
319 assert(Spill.size() == NumSubRegs); in restoreFromVGPRLane()
326 .addReg(Spill[I].VGPR) in restoreFromVGPRLane()
[all …]
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| H A D | SIMachineFunctionInfo.cpp | 487 auto &Spill = VGPRToAGPRSpills[FI]; in allocateVGPRSpillToAGPR() local
490 if (!Spill.Lanes.empty()) in allocateVGPRSpillToAGPR()
491 return Spill.FullyAllocated; in allocateVGPRSpillToAGPR()
495 Spill.Lanes.resize(NumLanes, AMDGPU::NoRegister); in allocateVGPRSpillToAGPR()
503 Spill.FullyAllocated = true; in allocateVGPRSpillToAGPR()
531 Spill.FullyAllocated = false; in allocateVGPRSpillToAGPR()
538 Spill.Lanes[I] = *NextSpillReg++; in allocateVGPRSpillToAGPR()
541 return Spill.FullyAllocated; in allocateVGPRSpillToAGPR()
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| H A D | SIInstrFormats.td | 50 field bit Spill = 0;
193 let TSFlags{26} = Spill;
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| H A D | SIRegisterInfo.cpp | 2063 SpilledReg Spill = VGPRSpills[i]; in spillSGPR() local
2073 SB.TII.get(AMDGPU::SI_SPILL_S32_TO_VGPR), Spill.VGPR) in spillSGPR()
2075 .addImm(Spill.Lane) in spillSGPR()
2076 .addReg(Spill.VGPR); in spillSGPR()
2180 SpilledReg Spill = VGPRSpills[i]; in restoreSGPR() local
2183 .addReg(Spill.VGPR) in restoreSGPR()
2184 .addImm(Spill.Lane); in restoreSGPR()
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| H A D | SIDefines.h | 93 Spill = 1 << 26, enumerator
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| H A D | SIInstrInfo.h | 774 return get(Opcode).TSFlags & SIInstrFlags::Spill; in isSpill()
778 return MI.getDesc().TSFlags & SIInstrFlags::Spill; in isSpill()
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| H A D | SIInstructions.td | 978 let UseNamedOperandTable = 1, Spill = 1, SALU = 1, Uses = [EXEC] in {
1014 let Spill = 1, VALU = 1, isConvergent = 1 in {
1036 } // End Spill = 1, VALU = 1, isConvergent = 1
1043 let UseNamedOperandTable = 1, Spill = 1, VALU = 1,
1073 } // End UseNamedOperandTable = 1, Spill = 1, VALU = 1, SchedRW = [WriteVMEM]
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| /freebsd/contrib/llvm-project/compiler-rt/lib/xray/ |
| H A D | xray_trampoline_powerpc64_asm.S | 8 # Spill r3-r10, f1-f13, and vsr34-vsr45, which are parameter registers.
149 # Spill r3-r4, f1-f8, and vsr34-vsr41, which are return registers.
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| /freebsd/contrib/llvm-project/lld/ELF/ |
| H A D | InputSection.h | 65 Spill, enumerator
427 s->kind() == SectionBase::Spill; in classof()
486 return sec->kind() == InputSectionBase::Spill; in classof()
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| H A D | InputSection.cpp | 206 case Spill: in getOffset()
382 source.addralign, source.addralign, {}, SectionBase::Spill), in PotentialSpillSection()
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| H A D | Options.td | 219 …HelpText<"Spill input sections to later matching output sections to avoid memory region overflow">;
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/LiveDebugValues/ |
| H A D | InstrRefBasedImpl.h | 804 unsigned getLocID(SpillLocationNo Spill, unsigned SpillSubReg) {
807 return getLocID(Spill, {Size, Offs});
813 unsigned getLocID(SpillLocationNo Spill, StackSlotPos Idx) {
814 unsigned SlotNo = Spill.id() - 1;
824 unsigned getSpillIDWithIdx(SpillLocationNo Spill, unsigned Idx) {
825 unsigned SlotNo = Spill.id() - 1;
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| H A D | InstrRefBasedImpl.cpp | 1278 const SpillLoc &Spill = SpillLocs[SpillID.id()]; in emitLoc() local
1279 unsigned Base = Spill.SpillBase; in emitLoc()
1330 TRI.getOffsetOpcodes(Spill.SpillOffset, OffsetOps); in emitLoc()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | FunctionLoweringInfo.h | 104 Spill, enumerator
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | StatepointLowering.cpp | 183 if (Record.type != RecordType::Spill) in findPreviousSpillSlot()
930 Record.type = RecordType::Spill; in LowerAsSTATEPOINT()
1259 if (Record.type == RecordType::Spill) { in visitGCRelocate()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrFP.td | 184 // Spill f16 to 4-byte spill slot.
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | Target.td | 80 int SpillSize = SS; // Spill slot size in bits.
81 int SpillAlignment = SA; // Spill slot alignment in bits.
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SMEInstrInfo.td | 232 // Spill + fill
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