Searched refs:SmallVT (Results 1 – 7 of 7) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 605 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits); in ShrinkDemandedOp() local
606 if (TLI.isTruncateFree(VT, SmallVT) && TLI.isZExtFree(SmallVT, VT)) { in ShrinkDemandedOp()
609 Op.getOpcode(), dl, SmallVT, in ShrinkDemandedOp()
610 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, Op.getOperand(0)), in ShrinkDemandedOp()
611 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, Op.getOperand(1))); in ShrinkDemandedOp()
1845 EVT SmallVT = EVT::getIntegerVT(*TLO.DAG.getContext(), SmallVTBits); in SimplifyDemandedBits() local
1846 if (isNarrowingProfitable(VT, SmallVT) && in SimplifyDemandedBits()
1847 isTypeDesirableForOp(ISD::SHL, SmallVT) && in SimplifyDemandedBits()
1848 isTruncateFree(VT, SmallVT) && isZExtFree(SmallVT, VT) && in SimplifyDemandedBits()
1849 (!TLO.LegalOperations() || isOperationLegal(ISD::SHL, SmallVT))) { in SimplifyDemandedBits()
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| H A D | LegalizeIntegerTypes.cpp | 1796 EVT SmallVT = LHS.getValueType(); in PromoteIntRes_XMULO() local
1818 unsigned Shift = SmallVT.getScalarSizeInBits(); in PromoteIntRes_XMULO()
1828 Mul, DAG.getValueType(SmallVT)); in PromoteIntRes_XMULO()
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| H A D | DAGCombiner.cpp | 10648 EVT SmallVT = N0.getOperand(0).getValueType(); in visitSRL() local
10649 unsigned BitSize = SmallVT.getScalarSizeInBits(); in visitSRL()
10653 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { in visitSRL()
10657 DAG.getNode(ISD::SRL, DL0, SmallVT, N0.getOperand(0), in visitSRL()
10658 DAG.getShiftAmountConstant(ShiftAmt, SmallVT, DL0)); in visitSRL()
24939 EVT SmallVT = V.getOperand(1).getValueType(); in visitEXTRACT_SUBVECTOR() local
24940 if (!NVT.bitsEq(SmallVT)) in visitEXTRACT_SUBVECTOR()
24949 if (InsIdx * SmallVT.getScalarSizeInBits() == in visitEXTRACT_SUBVECTOR()
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| H A D | SelectionDAGBuilder.cpp | 10396 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), Bits); in lowerRangeToAssertZExt() local
10401 DAG.getValueType(SmallVT)); in lowerRangeToAssertZExt()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 5186 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), WidthVal); in PerformDAGCombine() local
5195 DAG.getValueType(SmallVT)); in PerformDAGCombine()
5198 return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT); in PerformDAGCombine()
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| H A D | SIISelLowering.cpp | 8391 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), llvm::bit_width(MaxID)); in lowerWorkitemID() local
8393 DAG.getValueType(SmallVT)); in lowerWorkitemID()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 1047 for (auto SmallVT : SmallerVTs) { in RISCVTargetLowering() local
1048 setTruncStoreAction(VT, SmallVT, Expand); in RISCVTargetLowering()
1049 setLoadExtAction(ISD::EXTLOAD, VT, SmallVT, Expand); in RISCVTargetLowering()
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