Searched refs:ShiftWidth (Results 1 – 8 of 8) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelDAGToDAG.cpp | 271 bool LoongArchDAGToDAGISel::selectShiftMask(SDValue N, unsigned ShiftWidth, in selectShiftMask() argument
281 assert(isPowerOf2_32(ShiftWidth) && "Unexpected max shift amount!"); in selectShiftMask()
282 APInt ShMask(AndMask.getBitWidth(), ShiftWidth - 1); in selectShiftMask()
299 assert(isPowerOf2_32(ShiftWidth) && "Unexpected max shift amount!"); in selectShiftMask()
303 if (lsb == 0 && Log2_32(ShiftWidth) <= msb + 1) { in selectShiftMask()
312 if (Imm != 0 && Imm % ShiftWidth == 0) { in selectShiftMask()
|
| H A D | LoongArchISelDAGToDAG.h | 49 bool selectShiftMask(SDValue N, unsigned ShiftWidth, SDValue &ShAmt);
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVInstructionSelector.cpp | 97 unsigned ShiftWidth) const;
273 unsigned ShiftWidth) const { in selectShiftMask()
302 APInt ShMask(AndMask.getBitWidth(), ShiftWidth - 1); in selectShiftMask()
317 if (Imm != 0 && Imm.urem(ShiftWidth) == 0) in selectShiftMask()
322 if (Imm != 0 && Imm.urem(ShiftWidth) == 0) { in selectShiftMask()
333 if (Imm.urem(ShiftWidth) == ShiftWidth - 1) { in selectShiftMask()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.h | 89 bool selectShiftMask(SDValue N, unsigned ShiftWidth, SDValue &ShAmt);
|
| H A D | RISCVISelDAGToDAG.cpp | 3098 bool RISCVDAGToDAGISel::selectShiftMask(SDValue N, unsigned ShiftWidth, in selectShiftMask() argument
3115 assert(isPowerOf2_32(ShiftWidth) && "Unexpected max shift amount!"); in selectShiftMask()
3116 APInt ShMask(AndMask.getBitWidth(), ShiftWidth - 1); in selectShiftMask()
3135 if (Imm != 0 && Imm % ShiftWidth == 0) { in selectShiftMask()
3144 if (Imm != 0 && Imm % ShiftWidth == 0) { in selectShiftMask()
3156 if (Imm % ShiftWidth == ShiftWidth - 1) { in selectShiftMask()
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | PatternMatch.h | 2980 unsigned ShiftWidth = TypeSize - 1;
2993 auto LHS = m_AShr(m_Value(Op), m_SpecificInt(ShiftWidth));
2994 auto RHS = m_LShr(m_Neg(m_Deferred(Op)), m_SpecificInt(ShiftWidth));
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 1358 AArch64_AM::ShiftExtendType ShiftExtendTy, int ShiftWidth,
1368 bool MatchShift = getShiftExtendAmount() == Log2_32(ShiftWidth / 8); in isSVEDataVectorRegWithShiftExtend()
1371 !ShiftWidthAlwaysSame && hasShiftExtendAmount() && ShiftWidth == 8) in isSVEDataVectorRegWithShiftExtend()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBankInfo.cpp | 1561 auto ShiftWidth = B.buildShl(S32, WidthReg, B.buildConstant(S32, 16)); in applyMappingBFE() local
1566 auto MergedInputs = B.buildOr(S32, ClampOffset, ShiftWidth); in applyMappingBFE()
|