Searched refs:ShiftWidth (Results 1 – 8 of 8) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelDAGToDAG.cpp | 232 bool LoongArchDAGToDAGISel::selectShiftMask(SDValue N, unsigned ShiftWidth, in selectShiftMask() argument
242 assert(isPowerOf2_32(ShiftWidth) && "Unexpected max shift amount!"); in selectShiftMask()
243 APInt ShMask(AndMask.getBitWidth(), ShiftWidth - 1); in selectShiftMask()
260 assert(isPowerOf2_32(ShiftWidth) && "Unexpected max shift amount!"); in selectShiftMask()
264 if (lsb == 0 && Log2_32(ShiftWidth) <= msb + 1) { in selectShiftMask()
273 if (Imm != 0 && Imm % ShiftWidth == 0) { in selectShiftMask()
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| H A D | LoongArchISelDAGToDAG.h | 47 bool selectShiftMask(SDValue N, unsigned ShiftWidth, SDValue &ShAmt);
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVInstructionSelector.cpp | 170 unsigned ShiftWidth = ShiftLLT.getSizeInBits(); in selectShiftMask() local
171 assert(isPowerOf2_32(ShiftWidth) && "Unexpected max shift amount!"); in selectShiftMask()
195 APInt ShMask(AndMask.getBitWidth(), ShiftWidth - 1); in selectShiftMask()
210 if (Imm != 0 && Imm.urem(ShiftWidth) == 0) in selectShiftMask()
215 if (Imm != 0 && Imm.urem(ShiftWidth) == 0) { in selectShiftMask()
226 if (Imm.urem(ShiftWidth) == ShiftWidth - 1) { in selectShiftMask()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.h | 87 bool selectShiftMask(SDValue N, unsigned ShiftWidth, SDValue &ShAmt);
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| H A D | RISCVISelDAGToDAG.cpp | 2746 bool RISCVDAGToDAGISel::selectShiftMask(SDValue N, unsigned ShiftWidth, in selectShiftMask() argument
2763 assert(isPowerOf2_32(ShiftWidth) && "Unexpected max shift amount!"); in selectShiftMask()
2764 APInt ShMask(AndMask.getBitWidth(), ShiftWidth - 1); in selectShiftMask()
2783 if (Imm != 0 && Imm % ShiftWidth == 0) { in selectShiftMask()
2792 if (Imm != 0 && Imm % ShiftWidth == 0) { in selectShiftMask()
2804 if (Imm % ShiftWidth == ShiftWidth - 1) { in selectShiftMask()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | PatternMatch.h | 2813 unsigned ShiftWidth = TypeSize - 1;
2826 auto LHS = m_AShr(m_Value(OpL), m_SpecificInt(ShiftWidth));
2827 auto RHS = m_LShr(m_Neg(m_Value(OpR)), m_SpecificInt(ShiftWidth));
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 1336 AArch64_AM::ShiftExtendType ShiftExtendTy, int ShiftWidth,
1346 bool MatchShift = getShiftExtendAmount() == Log2_32(ShiftWidth / 8); in isSVEDataVectorRegWithShiftExtend()
1349 !ShiftWidthAlwaysSame && hasShiftExtendAmount() && ShiftWidth == 8) in isSVEDataVectorRegWithShiftExtend()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBankInfo.cpp | 1533 auto ShiftWidth = B.buildShl(S32, WidthReg, B.buildConstant(S32, 16)); in applyMappingBFE() local
1538 auto MergedInputs = B.buildOr(S32, ClampOffset, ShiftWidth); in applyMappingBFE()
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