| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 871 MVT ShiftVT = getScalarShiftAmountTy(DL, LHSTy); in getShiftAmountTy() local
874 if (ShiftVT.getSizeInBits() < Log2_32_Ceil(LHSTy.getSizeInBits())) in getShiftAmountTy()
875 ShiftVT = MVT::i32; in getShiftAmountTy()
876 assert(ShiftVT.getSizeInBits() >= Log2_32_Ceil(LHSTy.getSizeInBits()) && in getShiftAmountTy()
878 return ShiftVT; in getShiftAmountTy()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 4373 EVT ShiftVT = getShiftAmountTy(N0.getValueType()); in visitMUL() local
4374 SDValue Trunc = DAG.getZExtOrTrunc(LogBase2, DL, ShiftVT); in visitMUL()
4917 EVT ShiftVT = getShiftAmountTy(N0.getValueType()); in visitUDIVLike() local
4918 SDValue Trunc = DAG.getZExtOrTrunc(LogBase2, DL, ShiftVT); in visitUDIVLike()
5159 EVT ShiftVT = getShiftAmountTy(N0.getValueType()); in visitMULHU() local
5160 SDValue Trunc = DAG.getZExtOrTrunc(SRLAmt, DL, ShiftVT); in visitMULHU()
8162 EVT ShiftVT = OppShift.getOperand(1).getValueType(); in extractShiftForRotate() local
8164 SDValue NewShiftNode = DAG.getConstant(NeededShiftAmt, DL, ShiftVT); in extractShiftForRotate()
9838 EVT ShiftVT = C1->getValueType(0); in visitRotate() local
9841 SDValue BitsizeC = DAG.getConstant(Bitsize, dl, ShiftVT); in visitRotate()
[all …]
|
| H A D | LegalizeDAG.cpp | 1666 EVT ShiftVT = IntVT; in ExpandFCOPYSIGN() local
1670 ShiftVT = MagVT; in ExpandFCOPYSIGN()
1673 SDValue ShiftCnst = DAG.getConstant(ShiftAmount, DL, ShiftVT); in ExpandFCOPYSIGN()
1674 SignBit = DAG.getNode(ISD::SRL, DL, ShiftVT, SignBit, ShiftCnst); in ExpandFCOPYSIGN()
1676 SDValue ShiftCnst = DAG.getConstant(-ShiftAmount, DL, ShiftVT); in ExpandFCOPYSIGN()
1677 SignBit = DAG.getNode(ISD::SHL, DL, ShiftVT, SignBit, ShiftCnst); in ExpandFCOPYSIGN()
2749 EVT ShiftVT = TLI.getShiftAmountTy(SrcVT, DAG.getDataLayout()); in ExpandLegalINT_TO_FP() local
2750 SDValue ShiftConst = DAG.getConstant(1, dl, ShiftVT); in ExpandLegalINT_TO_FP()
|
| H A D | TargetLowering.cpp | 1735 EVT ShiftVT = Op1.getValueType(); in SimplifyDemandedBits() local
1758 SDValue NewSA = TLO.DAG.getConstant(Diff, dl, ShiftVT); in SimplifyDemandedBits()
1797 TLO.DAG.getConstant(ShAmt - InnerShAmt, dl, ShiftVT); in SimplifyDemandedBits()
1931 EVT ShiftVT = Op1.getValueType(); in SimplifyDemandedBits() local
1954 SDValue NewSA = TLO.DAG.getConstant(Diff, dl, ShiftVT); in SimplifyDemandedBits()
2023 EVT ShiftVT = Op1.getValueType(); in SimplifyDemandedBits() local
2105 SDValue NewSA = TLO.DAG.getConstant(BitWidth - 1 - Log2, dl, ShiftVT); in SimplifyDemandedBits()
8367 EVT ShiftVT = getShiftAmountTy(SrcVT, DAG.getDataLayout()); in expandUINT_TO_FP() local
8379 SDValue HiShift = DAG.getConstant(32, dl, ShiftVT); in expandUINT_TO_FP()
|
| H A D | SelectionDAG.cpp | 1758 EVT ShiftVT = TLI->getShiftAmountTy(VT, getDataLayout()); in getShiftAmountConstant() local
1759 return getConstant(Val, DL, ShiftVT); in getShiftAmountConstant()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 9314 MVT ShiftVT = widenMaskVectorType(ResVT, Subtarget); in LowerCONCAT_VECTORSvXi1() local
9315 Op = widenSubVector(ShiftVT, SubVec, false, Subtarget, DAG, dl); in LowerCONCAT_VECTORSvXi1()
9316 Op = DAG.getNode(X86ISD::KSHIFTL, dl, ShiftVT, Op, in LowerCONCAT_VECTORSvXi1()
11640 static int matchShuffleAsShift(MVT &ShiftVT, unsigned &Opcode, in matchShuffleAsShift() argument
11677 ShiftVT = ByteShift ? MVT::getVectorVT(MVT::i8, SizeInBits / 8) in matchShuffleAsShift()
11710 MVT ShiftVT; in lowerShuffleAsShift() local
11715 int ShiftAmt = matchShuffleAsShift(ShiftVT, Opcode, VT.getScalarSizeInBits(), in lowerShuffleAsShift()
11720 ShiftAmt = matchShuffleAsShift(ShiftVT, Opcode, VT.getScalarSizeInBits(), in lowerShuffleAsShift()
11731 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) && in lowerShuffleAsShift()
11733 V = DAG.getBitcast(ShiftVT, V); in lowerShuffleAsShift()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 6754 EVT ShiftVT = N0.getOperand(1).getValueType(); in combineSIGN_EXTEND() local
6759 ShiftVT)); in combineSIGN_EXTEND()
6761 DAG.getConstant(NewSraAmt, SDLoc(N0), ShiftVT)); in combineSIGN_EXTEND()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 6695 EVT ShiftVT = N->getOperand(1).getValueType(); in LowerShift() local
6697 ISD::SUB, dl, ShiftVT, getZeroVector(ShiftVT, DAG, dl), N->getOperand(1)); in LowerShift()
|