| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 970 MVT ShiftVT = getScalarShiftAmountTy(DL, LHSTy); in getShiftAmountTy() local
973 if (ShiftVT.getSizeInBits() < Log2_32_Ceil(LHSTy.getSizeInBits())) in getShiftAmountTy()
974 ShiftVT = MVT::i32; in getShiftAmountTy()
975 assert(ShiftVT.getSizeInBits() >= Log2_32_Ceil(LHSTy.getSizeInBits()) && in getShiftAmountTy()
977 return ShiftVT; in getShiftAmountTy()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 4703 EVT ShiftVT = getShiftAmountTy(N0.getValueType()); in visitMUL() local
4704 SDValue Trunc = DAG.getZExtOrTrunc(LogBase2, DL, ShiftVT); in visitMUL()
5261 EVT ShiftVT = getShiftAmountTy(N0.getValueType()); in visitUDIVLike() local
5262 SDValue Trunc = DAG.getZExtOrTrunc(LogBase2, DL, ShiftVT); in visitUDIVLike()
5503 EVT ShiftVT = getShiftAmountTy(N0.getValueType()); in visitMULHU() local
5504 SDValue Trunc = DAG.getZExtOrTrunc(SRLAmt, DL, ShiftVT); in visitMULHU()
8626 EVT ShiftVT = OppShift.getOperand(1).getValueType(); in extractShiftForRotate() local
8628 SDValue NewShiftNode = DAG.getConstant(NeededShiftAmt, DL, ShiftVT); in extractShiftForRotate()
10294 EVT ShiftVT = N1.getValueType(); in visitRotate() local
10297 SDValue BitsizeC = DAG.getConstant(Bitsize, dl, ShiftVT); in visitRotate()
[all …]
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| H A D | LegalizeDAG.cpp | 1733 EVT ShiftVT = IntVT; in ExpandFCOPYSIGN() local
1737 ShiftVT = MagVT; in ExpandFCOPYSIGN()
1740 SDValue ShiftCnst = DAG.getConstant(ShiftAmount, DL, ShiftVT); in ExpandFCOPYSIGN()
1741 SignBit = DAG.getNode(ISD::SRL, DL, ShiftVT, SignBit, ShiftCnst); in ExpandFCOPYSIGN()
1743 SDValue ShiftCnst = DAG.getConstant(-ShiftAmount, DL, ShiftVT); in ExpandFCOPYSIGN()
1744 SignBit = DAG.getNode(ISD::SHL, DL, ShiftVT, SignBit, ShiftCnst); in ExpandFCOPYSIGN()
2776 EVT ShiftVT = TLI.getShiftAmountTy(SrcVT, DAG.getDataLayout()); in ExpandLegalINT_TO_FP() local
2777 SDValue ShiftConst = DAG.getConstant(1, dl, ShiftVT); in ExpandLegalINT_TO_FP()
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| H A D | TargetLowering.cpp | 1782 EVT ShiftVT = Op1.getValueType(); in SimplifyDemandedBits() local
1805 SDValue NewSA = TLO.DAG.getConstant(Diff, dl, ShiftVT); in SimplifyDemandedBits()
1844 TLO.DAG.getConstant(ShAmt - InnerShAmt, dl, ShiftVT); in SimplifyDemandedBits()
1968 EVT ShiftVT = Op1.getValueType(); in SimplifyDemandedBits() local
1991 SDValue NewSA = TLO.DAG.getConstant(Diff, dl, ShiftVT); in SimplifyDemandedBits()
2007 SDValue NewSA = TLO.DAG.getConstant(Combined, dl, ShiftVT); in SimplifyDemandedBits()
2091 EVT ShiftVT = Op1.getValueType(); in SimplifyDemandedBits() local
2173 SDValue NewSA = TLO.DAG.getConstant(BitWidth - 1 - Log2, dl, ShiftVT); in SimplifyDemandedBits()
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| H A D | SelectionDAG.cpp | 1809 EVT ShiftVT = TLI->getShiftAmountTy(VT, getDataLayout()); in getShiftAmountConstant() local
1810 return getConstant(Val, DL, ShiftVT); in getShiftAmountConstant()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 955 static int matchShuffleAsShift(MVT &ShiftVT, unsigned &Opcode, in matchShuffleAsShift() argument
999 ShiftVT = ByteShift ? MVT::getVectorVT(MVT::i8, SizeInBits / 8) in matchShuffleAsShift()
1037 MVT ShiftVT; in lowerVECTOR_SHUFFLEAsShift() local
1042 int ShiftAmt = matchShuffleAsShift(ShiftVT, Opcode, VT.getScalarSizeInBits(), in lowerVECTOR_SHUFFLEAsShift()
1047 ShiftAmt = matchShuffleAsShift(ShiftVT, Opcode, VT.getScalarSizeInBits(), in lowerVECTOR_SHUFFLEAsShift()
1055 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) && in lowerVECTOR_SHUFFLEAsShift()
1057 V = DAG.getBitcast(ShiftVT, V); in lowerVECTOR_SHUFFLEAsShift()
1058 V = DAG.getNode(Opcode, DL, ShiftVT, V, in lowerVECTOR_SHUFFLEAsShift()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 9719 MVT ShiftVT = widenMaskVectorType(ResVT, Subtarget); in LowerCONCAT_VECTORSvXi1() local
9720 Op = widenSubVector(ShiftVT, SubVec, false, Subtarget, DAG, dl); in LowerCONCAT_VECTORSvXi1()
9721 Op = DAG.getNode(X86ISD::KSHIFTL, dl, ShiftVT, Op, in LowerCONCAT_VECTORSvXi1()
12130 static int matchShuffleAsShift(MVT &ShiftVT, unsigned &Opcode, in matchShuffleAsShift() argument
12167 ShiftVT = ByteShift ? MVT::getVectorVT(MVT::i8, SizeInBits / 8) in matchShuffleAsShift()
12200 MVT ShiftVT; in lowerShuffleAsShift() local
12205 int ShiftAmt = matchShuffleAsShift(ShiftVT, Opcode, VT.getScalarSizeInBits(), in lowerShuffleAsShift()
12210 ShiftAmt = matchShuffleAsShift(ShiftVT, Opcode, VT.getScalarSizeInBits(), in lowerShuffleAsShift()
12221 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) && in lowerShuffleAsShift()
12223 V = DAG.getBitcast(ShiftVT, V); in lowerShuffleAsShift()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 7796 EVT ShiftVT = N0.getOperand(1).getValueType(); in combineSIGN_EXTEND() local
7801 ShiftVT)); in combineSIGN_EXTEND()
7803 DAG.getConstant(NewSraAmt, SDLoc(N0), ShiftVT)); in combineSIGN_EXTEND()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 6761 EVT ShiftVT = N->getOperand(1).getValueType(); in LowerShift() local
6763 ISD::SUB, dl, ShiftVT, getZeroVector(ShiftVT, DAG, dl), N->getOperand(1)); in LowerShift()
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