Searched refs:ShiftRight (Results 1 – 6 of 6) sorted by relevance
| /freebsd/contrib/llvm-project/clang/include/clang/Basic/ |
| H A D | arm_immcheck_incl.td | 16 def ImmCheckCvt : ImmCheckType<8>; // 1..sizeinbits(elt) (same as ShiftRight)
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| /freebsd/contrib/llvm-project/llvm/lib/ExecutionEngine/RuntimeDyld/ |
| H A D | RuntimeDyldChecker.cpp | 113 ShiftRight enumerator
180 return std::make_pair(BinOpToken::ShiftRight, Expr.substr(2).ltrim()); in parseBinOpToken()
219 case BinOpToken::ShiftRight: in computeBinOpResult()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 1845 SDValue ShiftRight = Op.getOperand(0); in LowerTruncateToBTST() local
1846 return getBitTestCondition(ShiftRight.getOperand(0), ShiftRight.getOperand(1), in LowerTruncateToBTST()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 4633 unsigned ShiftRight = NumElems - SubVecNumElems - IdxVal; in insert1BitVector() local
4636 if (ShiftRight != 0) in insert1BitVector()
4638 DAG.getTargetConstant(ShiftRight, dl, MVT::i8)); in insert1BitVector()
4675 unsigned ShiftRight = NumElems - SubVecNumElems - IdxVal; in insert1BitVector() local
4687 DAG.getTargetConstant(ShiftRight, dl, MVT::i8)); in insert1BitVector()
4698 DAG.getTargetConstant(ShiftRight, dl, MVT::i8)); in insert1BitVector()
51748 if (SDValue ShiftRight = combineAndMaskToShift(N, dl, DAG, Subtarget)) in combineAnd() local
51749 return ShiftRight; in combineAnd()
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| /freebsd/sys/contrib/dev/acpica/ |
| H A D | changes.txt | 4316 ShiftRight. The actual problem cases seem to be rather unusual in common
4618 Z = X >> Y ShiftRight (X, Y, Z)
4647 X >>= Y ShiftRight (X, Y, X)
12274 Fixed a problem where a ShiftLeft or ShiftRight of more than 64 bits
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 10180 SDValue ShiftRight = in lowerEXTRACT_VECTOR_ELT() local
10182 SDValue Res = DAG.getNode(ISD::AND, DL, XLenVT, ShiftRight, in lowerEXTRACT_VECTOR_ELT()
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