Searched refs:ShiftOpcode (Results 1 – 7 of 7) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineShifts.cpp | 96 Instruction::BinaryOps ShiftOpcode = Sh0->getOpcode(); in reassociateShiftAmtsOfTwoSameDirectionShifts() local 147 BinaryOperator *NewShift = BinaryOperator::Create(ShiftOpcode, X, NewShAmt); in reassociateShiftAmtsOfTwoSameDirectionShifts() 153 if (ShiftOpcode == Instruction::BinaryOps::Shl) { in reassociateShiftAmtsOfTwoSameDirectionShifts() 363 Instruction::BinaryOps ShiftOpcode = I.getOpcode(); in foldShiftOfShiftedBinOp() local 367 ShiftOpcode != Instruction::Shl) in foldShiftOfShiftedBinOp() 378 return match(V, m_BinOp(ShiftOpcode, m_Value(X), m_Constant(C0))) && in foldShiftOfShiftedBinOp() 398 Value *NewShift1 = Builder.CreateBinOp(ShiftOpcode, X, ShiftSumC); in foldShiftOfShiftedBinOp() 399 Value *NewShift2 = Builder.CreateBinOp(ShiftOpcode, Y, C1); in foldShiftOfShiftedBinOp()
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| H A D | InstCombineCompares.cpp | 1706 unsigned ShiftOpcode = Shift->getOpcode(); in foldICmpAndShift() local 1707 bool IsShl = ShiftOpcode == Instruction::Shl; in foldICmpAndShift() 1712 if (ShiftOpcode == Instruction::Shl) { in foldICmpAndShift() 1723 } else if (ShiftOpcode == Instruction::LShr) { in foldICmpAndShift() 1736 assert(ShiftOpcode == Instruction::AShr && "Unknown shift opcode"); in foldICmpAndShift()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 6193 unsigned ShiftOpcode = ISD::DELETED_NODE; in Select() local 6209 ShiftOpcode = GET_ND_IF_ENABLED(X86::SHR64ri); in Select() 6217 ShiftOpcode = GET_ND_IF_ENABLED(X86::SHL64ri); in Select() 6226 ShiftOpcode = GET_ND_IF_ENABLED(X86::SHR64ri); in Select() 6232 ShiftOpcode = GET_ND_IF_ENABLED(X86::SHR64ri); in Select() 6238 ShiftOpcode = GET_ND_IF_ENABLED(X86::SHR64ri); in Select() 6245 if (ShiftOpcode != ISD::DELETED_NODE) { in Select() 6248 CurDAG->getMachineNode(ShiftOpcode, dl, MVT::i64, MVT::i32, in Select()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 1933 unsigned ShiftOpcode = MI.getOpcode(); in matchShiftOfShiftedLogic() local 1934 assert((ShiftOpcode == TargetOpcode::G_SHL || in matchShiftOfShiftedLogic() 1935 ShiftOpcode == TargetOpcode::G_ASHR || in matchShiftOfShiftedLogic() 1936 ShiftOpcode == TargetOpcode::G_LSHR || in matchShiftOfShiftedLogic() 1937 ShiftOpcode == TargetOpcode::G_USHLSAT || in matchShiftOfShiftedLogic() 1938 ShiftOpcode == TargetOpcode::G_SSHLSAT) && in matchShiftOfShiftedLogic() 1962 if (MI->getOpcode() != ShiftOpcode || in matchShiftOfShiftedLogic()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 2781 unsigned ShiftOpcode = Op.getOpcode(); in unrollVectorShift() local 2791 if (ShiftOpcode == ISD::SRA) in unrollVectorShift() 2795 DAG.getNode(ShiftOpcode, DL, MVT::i32, ShiftedValue, MaskedShiftValue)); in unrollVectorShift()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 7262 unsigned ShiftOpcode = ShiftOp.getOpcode(); in foldLogicOfShifts() local 7264 !(ShiftOpcode == ISD::SHL || ShiftOpcode == ISD::SRL || in foldLogicOfShifts() 7265 ShiftOpcode == ISD::SRA)) in foldLogicOfShifts() 7275 if (LogicOp.getOperand(0).getOpcode() == ShiftOpcode && in foldLogicOfShifts() 7279 } else if (LogicOp.getOperand(1).getOpcode() == ShiftOpcode && in foldLogicOfShifts() 7290 SDValue NewShift = DAG.getNode(ShiftOpcode, DL, VT, LogicX, Y); in foldLogicOfShifts() 10087 unsigned ShiftOpcode = Shift->getOpcode(); in combineShiftOfShiftedLogic() local 10094 if (V.getOpcode() != ShiftOpcode || !V.hasOneUse()) in combineShiftOfShiftedLogic() 10139 SDValue NewShift1 = DAG.getNode(ShiftOpcode, DL, VT, X, ShiftSumC); in combineShiftOfShiftedLogic() 10140 SDValue NewShift2 = DAG.getNode(ShiftOpcode, DL, VT, Y, C1); in combineShiftOfShiftedLogic() [all …]
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| H A D | TargetLowering.cpp | 2388 unsigned ShiftOpcode = NLZ > NTZ ? ISD::SRL : ISD::SHL; in SimplifyDemandedBits() local 2389 if (!TLO.LegalOperations() || isOperationLegal(ShiftOpcode, VT)) { in SimplifyDemandedBits() 2392 SDValue NewOp = TLO.DAG.getNode(ShiftOpcode, dl, VT, Src, ShAmt); in SimplifyDemandedBits()
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