Searched refs:ShiftLHS (Results 1 – 4 of 4) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerLowering.cpp | 847 MachineInstr *ShiftLHS = in getCmpOperandFoldingProfit() local
853 if (IsSupportedExtend(*ShiftLHS)) in getCmpOperandFoldingProfit()
|
| H A D | AArch64InstructionSelector.cpp | 7574 MachineOperand &ShiftLHS = ShiftInst->getOperand(1); in selectShiftedRegister() local
7575 Register ShiftReg = ShiftLHS.getReg(); in selectShiftedRegister()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 30361 unsigned ShiftLHS = IsROTL ? ISD::SHL : ISD::SRL; in LowerRotate() local
30375 DAG.getNode(ShiftLHS, DL, VT, R, DAG.getConstant(4, DL, VT)), in LowerRotate()
30385 DAG.getNode(ShiftLHS, DL, VT, R, DAG.getConstant(2, DL, VT)), in LowerRotate()
30395 DAG.getNode(ShiftLHS, DL, VT, R, DAG.getConstant(1, DL, VT)), in LowerRotate()
54560 SDValue ShiftLHS = Src.getOperand(0); in combineMOVMSK() local
54565 ShiftLHS = DAG.getBitcast(ShiftVT, ShiftLHS); in combineMOVMSK()
54568 ShiftLHS = getTargetVShiftByConstNode(X86ISD::VSHLI, DL, ShiftVT, in combineMOVMSK()
54569 ShiftLHS, ShiftAmt, DAG); in combineMOVMSK()
54572 ShiftLHS = DAG.getBitcast(SrcVT, ShiftLHS); in combineMOVMSK()
54574 SDValue Res = DAG.getNode(ISD::XOR, DL, SrcVT, ShiftLHS, ShiftRHS); in combineMOVMSK()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 17495 SDValue ShiftLHS = N->getOperand(0); in isDesirableToCommuteWithShift() local
17501 if (ShiftLHS.getOpcode() == ISD::AND && (VT == MVT::i32 || VT == MVT::i64) && in isDesirableToCommuteWithShift()
17502 isa<ConstantSDNode>(ShiftLHS.getOperand(1))) { in isDesirableToCommuteWithShift()
17503 uint64_t TruncMask = ShiftLHS.getConstantOperandVal(1); in isDesirableToCommuteWithShift()
17505 SDValue AndLHS = ShiftLHS.getOperand(0); in isDesirableToCommuteWithShift()
|