| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsExpandPseudo.cpp | 181 const unsigned ShiftImm = in expandAtomicCmpSwapSubword() local
185 .addImm(ShiftImm); in expandAtomicCmpSwapSubword()
188 .addImm(ShiftImm); in expandAtomicCmpSwapSubword()
490 const unsigned ShiftImm = SEOp == Mips::SEH ? 16 : 24; in expandAtomicBinOpSubword() local
494 .addImm(ShiftImm); in expandAtomicBinOpSubword()
497 .addImm(ShiftImm); in expandAtomicBinOpSubword()
592 const unsigned ShiftImm = SEOp == Mips::SEH ? 16 : 24; in expandAtomicBinOpSubword() local
595 .addImm(ShiftImm); in expandAtomicBinOpSubword()
598 .addImm(ShiftImm); in expandAtomicBinOpSubword()
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| H A D | MipsISelLowering.cpp | 1666 int64_t ShiftImm = 32 - (Size * 8); in emitSignExtendToI32InReg() local
1668 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm); in emitSignExtendToI32InReg()
1669 BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm); in emitSignExtendToI32InReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 215 uint64_t ShiftImm, bool SetFlags = false,
219 uint64_t ShiftImm, bool SetFlags = false,
246 AArch64_AM::ShiftExtendType ShiftType, uint64_t ShiftImm,
253 unsigned RHSReg, uint64_t ShiftImm);
1344 unsigned ShiftImm; in emitAddSub_ri() local
1346 ShiftImm = 0; in emitAddSub_ri()
1348 ShiftImm = 12; in emitAddSub_ri()
1377 .addImm(getShifterImm(AArch64_AM::LSL, ShiftImm)); in emitAddSub_ri()
1384 uint64_t ShiftImm, bool SetFlags, in emitAddSub_rs() argument
1394 if (ShiftImm >= RetVT.getSizeInBits()) in emitAddSub_rs()
[all …]
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| H A D | AArch64ISelDAGToDAG.cpp | 2550 uint64_t ShiftImm; in isBitfieldExtractOpFromSExtInReg() local
2551 if (!isOpcWithIntImmediate(Op.getNode(), ISD::SRL, ShiftImm) && in isBitfieldExtractOpFromSExtInReg()
2552 !isOpcWithIntImmediate(Op.getNode(), ISD::SRA, ShiftImm)) in isBitfieldExtractOpFromSExtInReg()
2556 if (ShiftImm + Width > BitWidth) in isBitfieldExtractOpFromSExtInReg()
2561 Immr = ShiftImm; in isBitfieldExtractOpFromSExtInReg()
2562 Imms = ShiftImm + Width - 1; in isBitfieldExtractOpFromSExtInReg()
2681 uint64_t ShiftImm; in tryBitfieldExtractOpFromSExt() local
2683 if (!isOpcWithIntImmediate(Op.getNode(), ISD::SRA, ShiftImm)) in tryBitfieldExtractOpFromSExt()
2689 unsigned Immr = ShiftImm; in tryBitfieldExtractOpFromSExt()
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| H A D | AArch64ISelLowering.cpp | 22381 unsigned ShiftImm = N->getConstantOperandVal(1); in performVectorShiftCombine() local
22382 assert(OpScalarSize > ShiftImm && "Invalid shift imm"); in performVectorShiftCombine()
22388 if (DCI.DAG.ComputeNumSignBits(Op.getOperand(0)) > ShiftImm) in performVectorShiftCombine()
22395 APInt ShiftedOutBits = APInt::getLowBitsSet(OpScalarSize, ShiftImm); in performVectorShiftCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 892 unsigned ShiftImm; // shift for OffsetReg. member
902 unsigned ShiftImm; member
914 unsigned ShiftImm; member
920 unsigned ShiftImm; member
1722 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 || in isMemTBH()
1741 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3) in isT2MemRegOffset()
1920 (Memory.ShiftType != ARM_AM::uxtw || Memory.ShiftImm != shift)) in isMemRegRQOffset()
2611 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); in addRegShiftedRegOperands()
2620 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm); in addRegShiftedImmOperands()
3025 Memory.ShiftImm, Memory.ShiftType); in addAddrMode2Operands()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 2783 unsigned ShiftImm; in SelectShift() local
2786 ShiftImm = CI->getZExtValue(); in SelectShift()
2790 if (ShiftImm == 0 || ShiftImm >=32) in SelectShift()
2814 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm)); in SelectShift()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCCodeEmitter.cpp | 937 // This value is encoded as follows, if ShiftImm is the value within those
938 // ranges then the encoding szimm5 = ShiftImm + size, where size is either 8
941 unsigned Size, ShiftImm; in getMVEShiftImmOpValue()
958 ShiftImm = MI.getOperand(OpIdx).getImm(); in getMVEShiftImmOpValue()
959 return Size + ShiftImm; in getMVEShiftImmOpValue()
952 unsigned Size, ShiftImm; getMVEShiftImmOpValue() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 1860 std::optional<int64_t> ShiftImm = getVectorShiftImm(Reg, MRI); in getVectorSHLImm() local
1861 if (!ShiftImm) in getVectorSHLImm()
1864 int64_t Imm = *ShiftImm; in getVectorSHLImm()
2405 int64_t ShiftImm; in earlySelect() local
2410 m_GOr(m_OneNonDBGUse(m_GShl(m_Reg(ShiftSrc), m_ICst(ShiftImm))), in earlySelect()
2414 if (ShiftImm > Size || ((1ULL << ShiftImm) - 1ULL) != uint64_t(MaskImm)) in earlySelect()
2417 int64_t Immr = Size - ShiftImm; in earlySelect()
2418 int64_t Imms = Size - ShiftImm - 1; in earlySelect()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCMIPeephole.cpp | 849 unsigned ShiftImm = DefMI->getOperand(3).getImm(); in simplifyCode() local
853 unsigned NewElem = (SplatImm + ShiftImm) & 0x3; in simplifyCode()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 4509 int64_t ShiftImm; in matchBitfieldExtractFromSExtInReg() local
4512 m_OneNonDBGUse(m_any_of(m_GAShr(m_Reg(ShiftSrc), m_ICst(ShiftImm)), in matchBitfieldExtractFromSExtInReg()
4513 m_GLShr(m_Reg(ShiftSrc), m_ICst(ShiftImm)))))) in matchBitfieldExtractFromSExtInReg()
4515 if (ShiftImm < 0 || ShiftImm + Width > Ty.getScalarSizeInBits()) in matchBitfieldExtractFromSExtInReg()
4519 auto Cst1 = B.buildConstant(ExtractTy, ShiftImm); in matchBitfieldExtractFromSExtInReg()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAG.cpp | 7054 const APInt &ShiftImm = N2C->getAPIntValue(); in getNode() local
7055 return getVScale(DL, VT, MulImm << ShiftImm); in getNode()
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