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Searched refs:ShiftImm (Results 1 – 12 of 12) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsExpandPseudo.cpp180 const unsigned ShiftImm = in expandAtomicCmpSwapSubword() local
184 .addImm(ShiftImm); in expandAtomicCmpSwapSubword()
187 .addImm(ShiftImm); in expandAtomicCmpSwapSubword()
510 const unsigned ShiftImm = SEOp == Mips::SEH ? 16 : 24; in expandAtomicBinOpSubword() local
514 .addImm(ShiftImm); in expandAtomicBinOpSubword()
517 .addImm(ShiftImm); in expandAtomicBinOpSubword()
682 const unsigned ShiftImm = SEOp == Mips::SEH ? 16 : 24; in expandAtomicBinOpSubword() local
685 .addImm(ShiftImm); in expandAtomicBinOpSubword()
688 .addImm(ShiftImm); in expandAtomicBinOpSubword()
H A DMipsISelLowering.cpp1761 int64_t ShiftImm = 32 - (Size * 8); in emitSignExtendToI32InReg() local
1763 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm); in emitSignExtendToI32InReg()
1764 BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm); in emitSignExtendToI32InReg()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp209 uint64_t ShiftImm, bool SetFlags = false,
213 uint64_t ShiftImm, bool SetFlags = false,
240 AArch64_AM::ShiftExtendType ShiftType, uint64_t ShiftImm,
247 Register RHSReg, uint64_t ShiftImm);
1339 unsigned ShiftImm; in emitAddSub_ri() local
1341 ShiftImm = 0; in emitAddSub_ri()
1343 ShiftImm = 12; in emitAddSub_ri()
1372 .addImm(getShifterImm(AArch64_AM::LSL, ShiftImm)); in emitAddSub_ri()
1379 uint64_t ShiftImm, bool SetFlags, in emitAddSub_rs() argument
1389 if (ShiftImm >= RetVT.getSizeInBits()) in emitAddSub_rs()
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H A DAArch64ISelDAGToDAG.cpp2650 uint64_t ShiftImm; in isBitfieldExtractOpFromSExtInReg() local
2651 if (!isOpcWithIntImmediate(Op.getNode(), ISD::SRL, ShiftImm) && in isBitfieldExtractOpFromSExtInReg()
2652 !isOpcWithIntImmediate(Op.getNode(), ISD::SRA, ShiftImm)) in isBitfieldExtractOpFromSExtInReg()
2656 if (ShiftImm + Width > BitWidth) in isBitfieldExtractOpFromSExtInReg()
2661 Immr = ShiftImm; in isBitfieldExtractOpFromSExtInReg()
2662 Imms = ShiftImm + Width - 1; in isBitfieldExtractOpFromSExtInReg()
2781 uint64_t ShiftImm; in tryBitfieldExtractOpFromSExt() local
2783 if (!isOpcWithIntImmediate(Op.getNode(), ISD::SRA, ShiftImm)) in tryBitfieldExtractOpFromSExt()
2789 unsigned Immr = ShiftImm; in tryBitfieldExtractOpFromSExt()
H A DAArch64ISelLowering.cpp23415 unsigned ShiftImm = N->getConstantOperandVal(1); in performVectorShiftCombine() local
23416 assert(OpScalarSize > ShiftImm && "Invalid shift imm"); in performVectorShiftCombine()
23422 if (DCI.DAG.ComputeNumSignBits(Op.getOperand(0)) > ShiftImm) in performVectorShiftCombine()
23429 APInt ShiftedOutBits = APInt::getLowBitsSet(OpScalarSize, ShiftImm); in performVectorShiftCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp892 unsigned ShiftImm; // shift for OffsetReg. member
902 unsigned ShiftImm; member
914 unsigned ShiftImm; member
920 unsigned ShiftImm; member
1723 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 || in isMemTBH()
1742 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3) in isT2MemRegOffset()
1921 (Memory.ShiftType != ARM_AM::uxtw || Memory.ShiftImm != shift)) in isMemRegRQOffset()
2612 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); in addRegShiftedRegOperands()
2621 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm); in addRegShiftedImmOperands()
3026 Memory.ShiftImm, Memory.ShiftType); in addAddrMode2Operands()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFastISel.cpp2850 unsigned ShiftImm; in SelectShift() local
2853 ShiftImm = CI->getZExtValue(); in SelectShift()
2857 if (ShiftImm == 0 || ShiftImm >=32) in SelectShift()
2884 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm)); in SelectShift()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCCodeEmitter.cpp948 unsigned Size, ShiftImm; in getMVEShiftImmOpValue() local
965 ShiftImm = MI.getOperand(OpIdx).getImm(); in getMVEShiftImmOpValue()
966 return Size + ShiftImm; in getMVEShiftImmOpValue()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp1868 std::optional<int64_t> ShiftImm = getVectorShiftImm(Reg, MRI); in getVectorSHLImm() local
1869 if (!ShiftImm) in getVectorSHLImm()
1872 int64_t Imm = *ShiftImm; in getVectorSHLImm()
2534 int64_t ShiftImm; in earlySelect() local
2539 m_GOr(m_OneNonDBGUse(m_GShl(m_Reg(ShiftSrc), m_ICst(ShiftImm))), in earlySelect()
2543 if (ShiftImm > Size || ((1ULL << ShiftImm) - 1ULL) != uint64_t(MaskImm)) in earlySelect()
2546 int64_t Immr = Size - ShiftImm; in earlySelect()
2547 int64_t Imms = Size - ShiftImm - 1; in earlySelect()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCMIPeephole.cpp844 unsigned ShiftImm = DefMI->getOperand(3).getImm(); in simplifyCode() local
848 unsigned NewElem = (SplatImm + ShiftImm) & 0x3; in simplifyCode()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp4635 int64_t ShiftImm; in matchBitfieldExtractFromSExtInReg() local
4638 m_OneNonDBGUse(m_any_of(m_GAShr(m_Reg(ShiftSrc), m_ICst(ShiftImm)), in matchBitfieldExtractFromSExtInReg()
4639 m_GLShr(m_Reg(ShiftSrc), m_ICst(ShiftImm)))))) in matchBitfieldExtractFromSExtInReg()
4641 if (ShiftImm < 0 || ShiftImm + Width > Ty.getScalarSizeInBits()) in matchBitfieldExtractFromSExtInReg()
4645 auto Cst1 = B.buildConstant(ExtractTy, ShiftImm); in matchBitfieldExtractFromSExtInReg()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp7601 const APInt &ShiftImm = N2C->getAPIntValue(); in getNode() local
7602 return getVScale(DL, VT, MulImm << ShiftImm); in getNode()