Searched refs:ShiftConst (Results 1 – 6 of 6) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Transforms/AggressiveInstCombine/ |
| H A D | AggressiveInstCombine.cpp | 574 uint64_t MulConst, ShiftConst; in tryToRecognizeTableBasedCttz() local
580 m_ConstantInt(ShiftConst))))) in tryToRecognizeTableBasedCttz()
588 if (InputBits - Log2_32(InputBits) != ShiftConst && in tryToRecognizeTableBasedCttz()
589 InputBits - Log2_32(InputBits) - 1 != ShiftConst) in tryToRecognizeTableBasedCttz()
592 if (!isCTTZTable(*ConstData, MulConst, ShiftConst, InputBits)) in tryToRecognizeTableBasedCttz()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXTargetTransformInfo.cpp | 400 if (const auto *ShiftConst = dyn_cast<ConstantInt>(II->getArgOperand(2))) { in convertNvvmIntrinsicToLlvm() local
402 if (ShiftConst->getZExtValue() >= II->getType()->getIntegerBitWidth()) in convertNvvmIntrinsicToLlvm()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeIntegerTypes.cpp | 733 auto ShiftConst = in PromoteIntRes_CTLZ() local
736 Op = DAG.getNode(ISD::SHL, dl, NVT, Op, ShiftConst); in PromoteIntRes_CTLZ()
742 Op = DAG.getNode(ISD::VP_SHL, dl, NVT, Op, ShiftConst, Mask, EVL); in PromoteIntRes_CTLZ()
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| H A D | LegalizeDAG.cpp | 2777 SDValue ShiftConst = DAG.getConstant(1, dl, ShiftVT); in ExpandLegalINT_TO_FP() local
2778 SDValue Shr = DAG.getNode(ISD::SRL, dl, SrcVT, Op0, ShiftConst); in ExpandLegalINT_TO_FP()
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| H A D | DAGCombiner.cpp | 3990 SDValue ShiftConst = DAG.getShiftAmountConstant(BitWidthDiff, VT, DL); in foldSubCtlzNot() local
3991 SDValue LShift = Matcher.getNode(ISD::SHL, DL, VT, Src, ShiftConst); in foldSubCtlzNot()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULegalizerInfo.cpp | 5697 auto ShiftConst = B.buildConstant(S32, 16); in legalizePointerAsRsrcIntrin() local
5698 ShiftedStride = B.buildShl(S32, ExtStride, ShiftConst); in legalizePointerAsRsrcIntrin()
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