| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineAndOrXor.cpp | 2400 const APInt *ShiftC; in visitAnd() local
2401 if (match(Op0, m_OneUse(m_SExt(m_AShr(m_Value(X), m_APInt(ShiftC))))) && in visitAnd()
2402 ShiftC->ult(Width)) { in visitAnd()
2403 if (*C == APInt::getLowBitsSet(Width, Width - ShiftC->getZExtValue())) { in visitAnd()
2407 Constant *ShAmtC = ConstantInt::get(Ty, ShiftC->zext(Width)); in visitAnd()
2414 if (match(Op0, m_AShr(m_Value(X), m_APInt(ShiftC))) && ShiftC->ult(Width) && in visitAnd()
2415 C->isMask(Width - ShiftC->getZExtValue())) in visitAnd()
2416 return BinaryOperator::CreateLShr(X, ConstantInt::get(Ty, *ShiftC)); in visitAnd()
2516 match(Op0, m_OneUse(m_LogicalShift(m_Power2(ShiftC), m_Value(X))))) { in visitAnd()
2517 int Log2ShiftC = ShiftC->exactLogBase2(); in visitAnd()
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| H A D | InstCombineSimplifyDemanded.cpp | 614 Constant *ShiftC = ConstantInt::get(VTy, CTZ); in SimplifyDemandedUseBits() local
615 Instruction *Shl = BinaryOperator::CreateShl(I->getOperand(0), ShiftC); in SimplifyDemandedUseBits()
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| H A D | InstCombineCompares.cpp | 1642 const APInt *ShiftC; in foldICmpXorShiftConst() local
1644 m_AShr(m_Deferred(X), m_APInt(ShiftC)))))) in foldICmpXorShiftConst()
1646 uint64_t Shift = ShiftC->getLimitedValue(); in foldICmpXorShiftConst()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 1616 if (ConstantSDNode *ShiftC = in SimplifyDemandedBits() local
1620 if (ShiftC->getAPIntValue().ult(BitWidth)) { in SimplifyDemandedBits()
1621 uint64_t ShiftAmt = ShiftC->getZExtValue(); in SimplifyDemandedBits()
8899 SDValue ShiftC = DAG.getShiftAmountConstant(Shift, VT, dl); in expandCTPOP() local
8901 DAG.getNode(ISD::SHL, dl, VT, V, ShiftC)); in expandCTPOP()
8966 SDValue ShiftC = DAG.getShiftAmountConstant(Shift, VT, dl); in expandVPCTPOP() local
8968 DAG.getNode(ISD::VP_SHL, dl, VT, V, ShiftC, Mask, VL), in expandVPCTPOP()
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| H A D | DAGCombiner.cpp | 10448 SDValue ShiftC = in visitSRA() local
10454 Add = DAG.getNode(ISD::ADD, DL, TruncVT, Trunc, ShiftC); in visitSRA()
10456 Add = DAG.getNode(ISD::SUB, DL, TruncVT, ShiftC, Trunc); in visitSRA()
14661 SDValue ShiftC = DAG.getConstant(ShiftedOffset, DL, VT); in reduceLoadWidth() local
14662 Result = DAG.getNode(ISD::SHL, DL, VT, Result, ShiftC); in reduceLoadWidth()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 6089 SDValue ShiftC = CurDAG->getTargetConstant(ShiftAmt, dl, MVT::i64); in Select() local
6092 N0.getOperand(0), ShiftC), in Select()
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| H A D | X86ISelLowering.cpp | 48283 auto *ShiftC = dyn_cast<ConstantSDNode>(N1); in combineShiftRightLogical() local
48285 if (!ShiftC || !AndC) in combineShiftRightLogical()
48300 APInt NewMaskVal = MaskVal.lshr(ShiftC->getAPIntValue()); in combineShiftRightLogical()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 6558 auto ShiftC = B.buildConstant(Ty, Shift); in lowerBitCount() local
6559 auto Shl = B.buildShl(Ty, ResTmp, ShiftC); in lowerBitCount()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 13848 auto *ShiftC = dyn_cast<ConstantSDNode>(N->getOperand(0).getOperand(1)); in isDesirableToCommuteXorWithShift() local
13849 if (XorC && ShiftC) { in isDesirableToCommuteXorWithShift()
13852 unsigned ShiftAmt = ShiftC->getZExtValue(); in isDesirableToCommuteXorWithShift()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 17528 auto *ShiftC = dyn_cast<ConstantSDNode>(N->getOperand(0).getOperand(1)); in isDesirableToCommuteXorWithShift() local
17529 if (XorC && ShiftC) { in isDesirableToCommuteXorWithShift()
17532 unsigned ShiftAmt = ShiftC->getZExtValue(); in isDesirableToCommuteXorWithShift()
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