| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.h | 468 SDValue Shift2 = DAG.getNode(ISD::SHL, DL, Ty, Add, Cst); in getAddrNonPICSym64() local
470 return DAG.getNode(ISD::ADD, DL, Ty, Shift2, in getAddrNonPICSym64()
|
| /freebsd/contrib/llvm-project/llvm/lib/Transforms/AggressiveInstCombine/ |
| H A D | AggressiveInstCombine.cpp | 735 uint64_t Shift1 = 0, Shift2 = 0; in foldLoadsRecursive() local
739 Shift2 = ShAmt2->getZExtValue(); in foldLoadsRecursive()
755 if ((Shift2 - Shift1) != ShiftDiff || (Offset2 - Offset1) != PrevSize) in foldLoadsRecursive()
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.h | 77 MachineInstr *Shift2; member
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/ObjectYAML/ |
| H A D | ELFYAML.h | 454 llvm::yaml::Hex32 Shift2; member
|
| /freebsd/contrib/llvm-project/lld/ELF/ |
| H A D | SyntheticSections.h | 703 enum { Shift2 = 26 }; enumerator
|
| H A D | SyntheticSections.cpp | 2416 write32(buf + 12, Shift2); in writeTo()
2427 val |= uint64_t(1) << ((sym.hash >> Shift2) % c); in writeTo()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 1917 MatchInfo.Shift2 = LogicMIOp1; in matchShiftOfShiftedLogic()
1920 MatchInfo.Shift2 = LogicMIOp2; in matchShiftOfShiftedLogic()
1947 Register Shift1Base = MatchInfo.Shift2->getOperand(1).getReg(); in applyShiftOfShiftedLogic()
1956 MatchInfo.Shift2->eraseFromParent(); in applyShiftOfShiftedLogic()
1959 Register Shift2 = Builder in applyShiftOfShiftedLogic() local
1965 Builder.buildInstr(MatchInfo.Logic->getOpcode(), {Dest}, {Shift1, Shift2}); in applyShiftOfShiftedLogic()
|
| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | InstructionSimplify.cpp | 2054 const APInt *Shift1, *Shift2; in simplifyAndCommutative() local
2056 match(Op1, m_Add(m_Shl(m_Specific(X), m_APInt(Shift2)), m_AllOnes())) && in simplifyAndCommutative()
2059 Shift1->uge(*Shift2)) in simplifyAndCommutative()
|
| /freebsd/contrib/llvm-project/llvm/lib/ObjectYAML/ |
| H A D | ELFEmitter.cpp | 1870 CBA.write<uint32_t>(Section.Header->Shift2, ELFT::Endianness); in writeSectionContent()
|
| H A D | ELFYAML.cpp | 1881 IO.mapRequired("Shift2", E.Shift2); in mapping()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.td | 5141 def Shift2 {
5147 dag Bits = (OR (AND Shift2.Right, MaskValues.Lo2),
5148 (AND Shift2.Left, MaskValues.Hi2));
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 29571 SDValue Shift2 = getTargetVShiftByConstNode(X86OpcI, dl, VT, R, in LowerShift() local
29573 return DAG.getVectorShuffle(VT, dl, Shift1, Shift2, ShuffleMask); in LowerShift()
47699 SDValue Shift2 = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), in combineMulSpecial() local
47701 return DAG.getNode(ISD::ADD, DL, VT, Shift1, Shift2); in combineMulSpecial()
48034 SDValue Shift2 = in combineMul() local
48037 NewMul = DAG.getNode(*Opc, DL, VT, Shift1, Shift2); in combineMul()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 14006 SDValue Shift2 = in expandMul()
14009 return DAG.getNode(ISD::SUB, DL, VT, Shift1, Shift2); in expandMul()
14003 SDValue Shift2 = expandMul() local
|