| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.h | 472 SDValue Shift2 = DAG.getNode(ISD::SHL, DL, Ty, Add, Cst); in getAddrNonPICSym64() local
474 return DAG.getNode(ISD::ADD, DL, Ty, Shift2, in getAddrNonPICSym64()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/AggressiveInstCombine/ |
| H A D | AggressiveInstCombine.cpp | 742 uint64_t Shift1 = 0, Shift2 = 0; in foldLoadsRecursive() local
746 Shift2 = ShAmt2->getZExtValue(); in foldLoadsRecursive()
762 if ((Shift2 - Shift1) != ShiftDiff || (Offset2 - Offset1) != PrevSize) in foldLoadsRecursive()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.h | 78 MachineInstr *Shift2; member
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| /freebsd/contrib/llvm-project/llvm/include/llvm/ObjectYAML/ |
| H A D | ELFYAML.h | 469 llvm::yaml::Hex32 Shift2; member
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 1985 MatchInfo.Shift2 = LogicMIOp1; in matchShiftOfShiftedLogic()
1988 MatchInfo.Shift2 = LogicMIOp2; in matchShiftOfShiftedLogic()
2015 Register Shift1Base = MatchInfo.Shift2->getOperand(1).getReg(); in applyShiftOfShiftedLogic()
2024 MatchInfo.Shift2->eraseFromParent(); in applyShiftOfShiftedLogic()
2027 Register Shift2 = Builder in applyShiftOfShiftedLogic() local
2033 Builder.buildInstr(MatchInfo.Logic->getOpcode(), {Dest}, {Shift1, Shift2}); in applyShiftOfShiftedLogic()
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| /freebsd/contrib/llvm-project/lld/ELF/ |
| H A D | SyntheticSections.h | 709 enum { Shift2 = 26 }; enumerator
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| H A D | SyntheticSections.cpp | 2480 write32(ctx, buf + 12, Shift2); in writeTo()
2491 val |= uint64_t(1) << ((sym.hash >> Shift2) % c); in writeTo()
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| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | InstructionSimplify.cpp | 2009 const APInt *Shift1, *Shift2; in simplifyAndCommutative() local
2011 match(Op1, m_Add(m_Shl(m_Specific(X), m_APInt(Shift2)), m_AllOnes())) && in simplifyAndCommutative()
2013 Shift1->uge(*Shift2)) in simplifyAndCommutative()
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| /freebsd/contrib/llvm-project/llvm/lib/ObjectYAML/ |
| H A D | ELFEmitter.cpp | 1897 CBA.write<uint32_t>(Section.Header->Shift2, ELFT::Endianness); in writeSectionContent()
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| H A D | ELFYAML.cpp | 1916 IO.mapRequired("Shift2", E.Shift2); in mapping()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.td | 5180 def Shift2 {
5186 dag Bits = (OR (AND Shift2.Right, MaskValues.Lo2),
5187 (AND Shift2.Left, MaskValues.Hi2));
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 30602 SDValue Shift2 = in LowerShift() local
30604 return DAG.getVectorShuffle(VT, dl, Shift1, Shift2, ShuffleMask); in LowerShift()
49470 SDValue Shift2 = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), in combineMulSpecial() local
49472 return DAG.getNode(ISD::ADD, DL, VT, Shift1, Shift2); in combineMulSpecial()
49796 SDValue Shift2 = in combineMul() local
49799 NewMul = DAG.getNode(*Opc, DL, VT, Shift1, Shift2); in combineMul()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 15985 SDValue Shift2 = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), in expandMulToAddOrSubOfShl() local
15987 return DAG.getNode(Op, DL, VT, Shift1, Shift2); in expandMulToAddOrSubOfShl()
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