| /freebsd/contrib/llvm-project/llvm/lib/Transforms/AggressiveInstCombine/ |
| H A D | AggressiveInstCombine.cpp | 742 uint64_t Shift1 = 0, Shift2 = 0; in foldLoadsRecursive() local
744 Shift1 = ShAmt1->getZExtValue(); in foldLoadsRecursive()
762 if ((Shift2 - Shift1) != ShiftDiff || (Offset2 - Offset1) != PrevSize) in foldLoadsRecursive()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 835 bool Shift1 = mi_match( in selectG_BUILD_VECTOR() local
839 if (Shift0 && Shift1) { in selectG_BUILD_VECTOR()
843 } else if (Shift1) { in selectG_BUILD_VECTOR()
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| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | InstructionSimplify.cpp | 2009 const APInt *Shift1, *Shift2; in simplifyAndCommutative() local
2010 if (match(Op0, m_Shl(m_Value(X), m_APInt(Shift1))) && in simplifyAndCommutative()
2013 Shift1->uge(*Shift2)) in simplifyAndCommutative()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 15983 SDValue Shift1 = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), in expandMulToAddOrSubOfShl() local
15987 return DAG.getNode(Op, DL, VT, Shift1, Shift2); in expandMulToAddOrSubOfShl()
16077 SDValue Shift1 = in expandMul() local
16080 DAG.getConstant(ScaleShift, DL, VT), Shift1); in expandMul()
16110 SDValue Shift1 = in expandMul() local
16112 return DAG.getNode(ISD::ADD, DL, VT, Shift1, in expandMul()
16122 SDValue Shift1 = in expandMul() local
16128 return DAG.getNode(ISD::SUB, DL, VT, Shift1, Mul359); in expandMul()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.td | 5170 def Shift1 {
5176 dag Bit = (OR (AND Shift1.Right, MaskValues.Lo1),
5177 (AND Shift1.Left, MaskValues.Hi1));
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 2016 Register Shift1 = in applyShiftOfShiftedLogic() local
2033 Builder.buildInstr(MatchInfo.Logic->getOpcode(), {Dest}, {Shift1, Shift2}); in applyShiftOfShiftedLogic()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 8062 SDValue Shift1 = N1.getOperand(0); in matchBSwapHWordOrAndAnd() local
8063 if (Shift0.getOpcode() != ISD::SHL || Shift1.getOpcode() != ISD::SRL) in matchBSwapHWordOrAndAnd()
8066 ConstantSDNode *ShiftAmt1 = isConstOrConstSplat(Shift1.getOperand(1)); in matchBSwapHWordOrAndAnd()
8071 if (Shift0.getOperand(0) != Shift1.getOperand(0)) in matchBSwapHWordOrAndAnd()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 30600 SDValue Shift1 = in LowerShift() local
30604 return DAG.getVectorShuffle(VT, dl, Shift1, Shift2, ShuffleMask); in LowerShift()
49468 SDValue Shift1 = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), in combineMulSpecial() local
49472 return DAG.getNode(ISD::ADD, DL, VT, Shift1, Shift2); in combineMulSpecial()
49793 SDValue Shift1 = in combineMul() local
49799 NewMul = DAG.getNode(*Opc, DL, VT, Shift1, Shift2); in combineMul()
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