| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsAnalyzeImmediate.cpp | 46 unsigned Shamt = llvm::countr_zero(Imm); in GetInstSeqLsSLL() local
47 GetInstSeqLs(Imm >> Shamt, RemSize - Shamt, SeqLs); in GetInstSeqLsSLL()
48 AddInstr(SeqLs, Inst(SLL, Shamt)); in GetInstSeqLsSLL()
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| H A D | MipsISelLowering.cpp | 915 unsigned Shamt = CN->getZExtValue(); in performORCombine() local
920 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits())) in performORCombine()
2608 SDValue Shamt = Op.getOperand(2); in lowerShiftLeftParts() local
2616 DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, in lowerShiftLeftParts()
2621 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt); in lowerShiftLeftParts()
2623 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt); in lowerShiftLeftParts()
2624 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, in lowerShiftLeftParts()
2638 SDValue Shamt = Op.getOperand(2); in lowerShiftRightParts() local
2655 DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, in lowerShiftRightParts()
2660 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt); in lowerShiftRightParts()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 2529 SDValue Shamt = Op.getOperand(2); in lowerShiftLeftParts() local
2543 SDValue ShamtMinusGRLen = DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusGRLen); in lowerShiftLeftParts()
2544 SDValue GRLenMinus1Shamt = DAG.getNode(ISD::XOR, DL, VT, Shamt, GRLenMinus1); in lowerShiftLeftParts()
2546 SDValue LoTrue = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt); in lowerShiftLeftParts()
2550 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt); in lowerShiftLeftParts()
2569 SDValue Shamt = Op.getOperand(2); in lowerShiftRightParts() local
2594 SDValue ShamtMinusGRLen = DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusGRLen); in lowerShiftRightParts()
2595 SDValue GRLenMinus1Shamt = DAG.getNode(ISD::XOR, DL, VT, Shamt, GRLenMinus1); in lowerShiftRightParts()
2597 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt); in lowerShiftRightParts()
2602 SDValue HiTrue = DAG.getNode(ShiftRightOp, DL, VT, Hi, Shamt); in lowerShiftRightParts()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 3435 SDValue Shamt = Op.getOperand(2); in LowerShiftLeftParts() local
3450 DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusRegisterSize); in LowerShiftLeftParts()
3452 DAG.getNode(ISD::XOR, DL, VT, RegisterSizeMinus1, Shamt); in LowerShiftLeftParts()
3454 SDValue LoTrue = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt); in LowerShiftLeftParts()
3458 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt); in LowerShiftLeftParts()
3476 SDValue Shamt = Op.getOperand(2); in LowerShiftRightParts() local
3502 DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusRegisterSize); in LowerShiftRightParts()
3504 DAG.getNode(ISD::XOR, DL, VT, RegisterSizeMinus1, Shamt); in LowerShiftRightParts()
3506 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt); in LowerShiftRightParts()
3511 SDValue HiTrue = DAG.getNode(ShiftRightOp, DL, VT, Hi, Shamt); in LowerShiftRightParts()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 7967 SDValue Shamt = Op.getOperand(2); in lowerShiftLeftParts()
7970 // if Shamt-XLEN < 0: // Shamt < XLEN in lowerShiftLeftParts()
7971 // Lo = Lo << Shamt in lowerShiftLeftParts()
7972 // Hi = (Hi << Shamt) | ((Lo >>u 1) >>u (XLEN-1 - Shamt)) in lowerShiftLeftParts()
7975 // Hi = Lo << (Shamt-XLEN) in lowerShiftLeftParts()
7981 SDValue ShamtMinusXLen = DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusXLen); in lowerShiftLeftParts()
7982 SDValue XLenMinus1Shamt = DAG.getNode(ISD::SUB, DL, VT, XLenMinus1, Shamt); in lowerShiftLeftParts()
7984 SDValue LoTrue = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt); in lowerShiftLeftParts()
7965 SDValue Shamt = Op.getOperand(2); lowerShiftLeftParts() local
8004 SDValue Shamt = Op.getOperand(2); lowerShiftRightParts() local
[all...] |