| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/ |
| H A D | VNCoercion.cpp | 382 Value *ShVal = Builder.CreateShl( in getMemInstValueForLoad() local
384 Val = Builder.CreateOr(Val, ShVal); in getMemInstValueForLoad()
390 Value *ShVal = in getMemInstValueForLoad() local
392 Val = Builder.CreateOr(OneElt, ShVal); in getMemInstValueForLoad()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | IntrinsicLowering.cpp | 193 Value *ShVal = ConstantInt::get(V->getType(), i); in LowerCTLZ() local
194 ShVal = Builder.CreateLShr(V, ShVal, "ctlz.sh"); in LowerCTLZ()
195 V = Builder.CreateOr(V, ShVal, "ctlz.step"); in LowerCTLZ()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonLoopIdiomRecognition.cpp | 1433 Value *ShAmt = CIV, *ShVal = Op; in convertShiftsToLeft() local
1434 auto *VTy = cast<IntegerType>(ShVal->getType()); in convertShiftsToLeft()
1437 ShVal = IRB.CreateShl(Op, ConstantInt::get(VTy, 1)); in convertShiftsToLeft()
1442 ShVal = upcast(CastMap, IRB, ShVal, ATy); in convertShiftsToLeft()
1447 W = IRB.CreateShl(ShVal, ShAmt); in convertShiftsToLeft()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 2419 SDValue ShVal = AddSrc.getOperand(0); in matchIndexRecursively() local
2426 CurDAG->MaskedValueIsZero(ShVal, HiBits))) { in matchIndexRecursively()
2428 SDValue ExtShVal = CurDAG->getNode(Opc, DL, VT, ShVal); in matchIndexRecursively()
2532 SDValue ShVal = N.getOperand(0); in matchAddressRecursively() local
2534 AM.IndexReg = matchIndexRecursively(ShVal, AM, Depth + 1); in matchAddressRecursively()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 613 unsigned ShVal = AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt); in SelectArithImmed() local
616 Shift = CurDAG->getTargetConstant(ShVal, dl, MVT::i32); in SelectArithImmed()
797 unsigned ShVal = AArch64_AM::getShifterImm(AArch64_AM::LSL, LowZBits); in SelectShiftedRegisterFromAnd() local
798 Shift = CurDAG->getTargetConstant(ShVal, DL, MVT::i32); in SelectShiftedRegisterFromAnd()
896 unsigned ShVal = AArch64_AM::getShifterImm(ShType, Val); in SelectShiftedRegister() local
899 Shift = CurDAG->getTargetConstant(ShVal, SDLoc(N), MVT::i32); in SelectShiftedRegister()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 2604 uint64_t ShVal = *ShAmtC; in SimplifyDemandedBits() local
2608 HighBits.lshrInPlace(ShVal); in SimplifyDemandedBits()
2613 SDValue NewShAmt = TLO.DAG.getShiftAmountConstant(ShVal, VT, dl); in SimplifyDemandedBits()
2703 unsigned ShVal = Op.getValueSizeInBits() - 1; in SimplifyDemandedBits() local
2704 SDValue ShAmt = TLO.DAG.getConstant(ShVal, dl, VT); in SimplifyDemandedBits()
8093 SDValue ShVal; in expandROT() local
8100 ShVal = DAG.getNode(ShOpc, DL, VT, Op0, ShAmt); in expandROT()
8108 ShVal = DAG.getNode(ShOpc, DL, VT, Op0, ShAmt); in expandROT()
8114 return DAG.getNode(ISD::OR, DL, VT, ShVal, HsVal); in expandROT()
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| H A D | DAGCombiner.cpp | 14112 SDValue ShVal = N0.getOperand(0); in visitZERO_EXTEND() local
14115 if (ShVal.getOpcode() == ISD::ZERO_EXTEND && N0.hasOneUse()) { in visitZERO_EXTEND()
14119 unsigned KnownZeroBits = ShVal.getValueSizeInBits() - in visitZERO_EXTEND()
14120 ShVal.getOperand(0).getValueSizeInBits(); in visitZERO_EXTEND()
14126 APInt::getHighBitsSet(ShVal.getValueSizeInBits(), in visitZERO_EXTEND()
14130 if (!DAG.MaskedValueIsZero(ShVal, ShiftOutMask)) in visitZERO_EXTEND()
14140 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, ShVal), ShAmt); in visitZERO_EXTEND()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 6851 Register ShVal; in lowerRotate() local
6858 ShVal = MIRBuilder.buildInstr(ShOpc, {DstTy}, {Src, ShAmt}).getReg(0); in lowerRotate()
6867 ShVal = MIRBuilder.buildInstr(ShOpc, {DstTy}, {Src, ShAmt}).getReg(0); in lowerRotate()
6874 MIRBuilder.buildOr(Dst, ShVal, RevShiftVal); in lowerRotate()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 6928 unsigned ShVal = AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt); in select12BitValueWithLeftShift() local
6931 [=](MachineInstrBuilder &MIB) { MIB.addImm(ShVal); }, in select12BitValueWithLeftShift()
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