Home
last modified time | relevance | path

Searched refs:ShTy (Results 1 – 4 of 4) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp3263 EVT ShTy = Amt.getValueType(); in ExpandShiftWithKnownAmountBit() local
3264 unsigned ShBits = ShTy.getScalarSizeInBits(); in ExpandShiftWithKnownAmountBit()
3285 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt, in ExpandShiftWithKnownAmountBit()
3286 DAG.getConstant(~HighBitMask, dl, ShTy)); in ExpandShiftWithKnownAmountBit()
3300 DAG.getConstant(NVTBits - 1, dl, ShTy)); in ExpandShiftWithKnownAmountBit()
3312 SDValue Amt2 = DAG.getNode(ISD::XOR, dl, ShTy, Amt, in ExpandShiftWithKnownAmountBit()
3313 DAG.getConstant(NVTBits - 1, dl, ShTy)); in ExpandShiftWithKnownAmountBit()
3329 SDValue Sh1 = DAG.getNode(Op2, dl, NVT, InL, DAG.getConstant(1, dl, ShTy)); in ExpandShiftWithKnownAmountBit()
3350 EVT ShTy = Amt.getValueType(); in ExpandShiftWithUnknownAmountBit() local
3360 SDValue NVBitsNode = DAG.getConstant(NVTBits, dl, ShTy); in ExpandShiftWithUnknownAmountBit()
[all …]
H A DSelectionDAG.cpp2466 EVT ShTy = TLI->getShiftAmountTy(LHSTy, getDataLayout()); in getShiftAmountOperand() local
2467 if (OpTy == ShTy || OpTy.isVector()) return Op; in getShiftAmountOperand()
2469 return getZExtOrTrunc(Op, SDLoc(Op), ShTy); in getShiftAmountOperand()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp7277 LLT ShTy = MRI.getType(Z); in lowerFunnelShiftWithInverse() local
7290 auto Zero = MIRBuilder.buildConstant(ShTy, 0); in lowerFunnelShiftWithInverse()
7295 auto One = MIRBuilder.buildConstant(ShTy, 1); in lowerFunnelShiftWithInverse()
7304 Z = MIRBuilder.buildNot(ShTy, Z).getReg(0); in lowerFunnelShiftWithInverse()
7316 LLT ShTy = MRI.getType(Z); in lowerFunnelShiftAsShifts() local
7329 auto BitWidthC = MIRBuilder.buildConstant(ShTy, BW); in lowerFunnelShiftAsShifts()
7330 ShAmt = MIRBuilder.buildURem(ShTy, Z, BitWidthC).getReg(0); in lowerFunnelShiftAsShifts()
7331 InvShAmt = MIRBuilder.buildSub(ShTy, BitWidthC, ShAmt).getReg(0); in lowerFunnelShiftAsShifts()
7337 auto Mask = MIRBuilder.buildConstant(ShTy, BW - 1); in lowerFunnelShiftAsShifts()
7340 ShAmt = MIRBuilder.buildAnd(ShTy, Z, Mask).getReg(0); in lowerFunnelShiftAsShifts()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp3717 CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, MCRegister SrcReg, in CreateShiftedRegister() argument
3721 Op->RegShiftedReg.ShiftTy = ShTy; in CreateShiftedRegister()
3731 CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, MCRegister SrcReg, in CreateShiftedImmediate() argument
3735 Op->RegShiftedImm.ShiftTy = ShTy; in CreateShiftedImmediate()