| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegBankCombiner.cpp | 369 unsigned ShOpc = MI.getOpcode(); in applyCanonicalizeZextShiftAmt() local
370 assert(ShOpc == AMDGPU::G_SHL || ShOpc == AMDGPU::G_LSHR || in applyCanonicalizeZextShiftAmt()
371 ShOpc == AMDGPU::G_ASHR); in applyCanonicalizeZextShiftAmt()
387 B.buildInstr(ShOpc, {ShDst}, {ShSrc, And}); in applyCanonicalizeZextShiftAmt()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMInstPrinter.cpp | 50 static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc, in printRegImmShift() argument
52 if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm)) in printRegImmShift()
56 assert(!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0"); in printRegImmShift()
57 O << getShiftOpcStr(ShOpc); in printRegImmShift()
59 if (ShOpc != ARM_AM::rrx) { in printRegImmShift()
434 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm()); in printSORegRegOperand() local
435 O << ", " << ARM_AM::getShiftOpcStr(ShOpc); in printSORegRegOperand()
436 if (ShOpc == ARM_AM::rrx) in printSORegRegOperand()
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| H A D | ARMMCCodeEmitter.cpp | 246 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const { in getShiftOp()
247 switch (ShOpc) { in getShiftOp()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstructionCombining.cpp | 924 unsigned ShOpc) { in foldBinOpShiftWithShift() argument
925 assert(ShOpc != Instruction::AShr); in foldBinOpShiftWithShift()
927 ShOpc == Instruction::Shl; in foldBinOpShiftWithShift()
930 auto GetInvShift = [](unsigned ShOpc) { in foldBinOpShiftWithShift() argument
931 assert(ShOpc != Instruction::AShr); in foldBinOpShiftWithShift()
932 return ShOpc == Instruction::LShr ? Instruction::Shl : Instruction::LShr; in foldBinOpShiftWithShift()
936 unsigned ShOpc, Constant *CMask, in foldBinOpShiftWithShift()
944 if (!IsCompletelyDistributable(BinOpc1, BinOpc2, ShOpc)) in foldBinOpShiftWithShift()
956 ConstantFoldBinaryOpOperands(GetInvShift(ShOpc), CMask, CShift, DL); in foldBinOpShiftWithShift()
957 return ConstantFoldBinaryOpOperands(ShOpc, MaskInvShift, CShift, DL) == in foldBinOpShiftWithShift()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.cpp | 584 unsigned ShOpc = SignExt ? RISCV::SLLIW : RISCV::SLLI; in tryShrinkShlLogicImm() local
590 CurDAG->getMachineNode(ShOpc, DL, VT, SDValue(BinOp, 0), in tryShrinkShlLogicImm()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 3373 SDValue ShOpc = in tryV6T2BitfieldExtractOp() local
3376 SDValue Ops[] = { N->getOperand(0).getOperand(0), ShOpc, in tryV6T2BitfieldExtractOp()
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| H A D | ARMISelLowering.cpp | 6782 unsigned ShOpc = N->getOpcode(); in Expand64BitShift() local
6798 if (ShOpc == ISD::SRL) { in Expand64BitShift()
6807 } else if (ShOpc == ISD::SRA) in Expand64BitShift()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 7537 unsigned ShOpc = IsLeft ? TargetOpcode::G_SHL : TargetOpcode::G_LSHR; in lowerRotate() local
7547 ShVal = MIRBuilder.buildInstr(ShOpc, {DstTy}, {Src, ShAmt}).getReg(0); in lowerRotate()
7556 ShVal = MIRBuilder.buildInstr(ShOpc, {DstTy}, {Src, ShAmt}).getReg(0); in lowerRotate()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 8308 unsigned ShOpc = IsLeft ? ISD::SHL : ISD::SRL; in expandROT() local
8318 ShVal = DAG.getNode(ShOpc, DL, VT, Op0, ShAmt); in expandROT()
8326 ShVal = DAG.getNode(ShOpc, DL, VT, Op0, ShAmt); in expandROT()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 30846 unsigned ShOpc = ConstantAmt ? Opc : X86OpcV; in LowerShift() local
30847 SDValue R0 = DAG.getNode(ShOpc, dl, VT, R, DAG.getBitcast(VT, Amt0)); in LowerShift()
30848 SDValue R1 = DAG.getNode(ShOpc, dl, VT, R, DAG.getBitcast(VT, Amt1)); in LowerShift()
30849 SDValue R2 = DAG.getNode(ShOpc, dl, VT, R, DAG.getBitcast(VT, Amt2)); in LowerShift()
30850 SDValue R3 = DAG.getNode(ShOpc, dl, VT, R, DAG.getBitcast(VT, Amt3)); in LowerShift()
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