| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMInstPrinter.cpp | 52 static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc, in printRegImmShift() argument
54 if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm)) in printRegImmShift()
58 assert(!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0"); in printRegImmShift()
59 O << getShiftOpcStr(ShOpc); in printRegImmShift()
61 if (ShOpc != ARM_AM::rrx) { in printRegImmShift()
436 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm()); in printSORegRegOperand() local
437 O << ", " << ARM_AM::getShiftOpcStr(ShOpc); in printSORegRegOperand()
438 if (ShOpc == ARM_AM::rrx) in printSORegRegOperand()
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| H A D | ARMMCCodeEmitter.cpp | 248 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const { in getShiftOp()
249 switch (ShOpc) { in getShiftOp()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstructionCombining.cpp | 895 unsigned ShOpc) { in foldBinOpShiftWithShift() argument
896 assert(ShOpc != Instruction::AShr); in foldBinOpShiftWithShift()
898 ShOpc == Instruction::Shl; in foldBinOpShiftWithShift()
901 auto GetInvShift = [](unsigned ShOpc) { in foldBinOpShiftWithShift() argument
902 assert(ShOpc != Instruction::AShr); in foldBinOpShiftWithShift()
903 return ShOpc == Instruction::LShr ? Instruction::Shl : Instruction::LShr; in foldBinOpShiftWithShift()
907 unsigned ShOpc, Constant *CMask, in foldBinOpShiftWithShift()
915 if (!IsCompletelyDistributable(BinOpc1, BinOpc2, ShOpc)) in foldBinOpShiftWithShift()
927 ConstantFoldBinaryOpOperands(GetInvShift(ShOpc), CMask, CShift, DL); in foldBinOpShiftWithShift()
928 return ConstantFoldBinaryOpOperands(ShOpc, MaskInvShift, CShift, DL) == in foldBinOpShiftWithShift()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.cpp | 670 unsigned ShOpc = SignExt ? RISCV::SLLIW : RISCV::SLLI; in tryShrinkShlLogicImm() local
676 CurDAG->getMachineNode(ShOpc, DL, VT, SDValue(BinOp, 0), in tryShrinkShlLogicImm()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 236 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); in convertToThreeAddress() local
237 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); in convertToThreeAddress()
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| H A D | ARMISelDAGToDAG.cpp | 3382 SDValue ShOpc = in tryV6T2BitfieldExtractOp() local
3385 SDValue Ops[] = { N->getOperand(0).getOperand(0), ShOpc, in tryV6T2BitfieldExtractOp()
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| H A D | ARMISelLowering.cpp | 6716 unsigned ShOpc = N->getOpcode(); in Expand64BitShift() local
6732 if (ShOpc == ISD::SRL) { in Expand64BitShift()
6741 } else if (ShOpc == ISD::SRA) in Expand64BitShift()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 6848 unsigned ShOpc = IsLeft ? TargetOpcode::G_SHL : TargetOpcode::G_LSHR; in lowerRotate() local
6858 ShVal = MIRBuilder.buildInstr(ShOpc, {DstTy}, {Src, ShAmt}).getReg(0); in lowerRotate()
6867 ShVal = MIRBuilder.buildInstr(ShOpc, {DstTy}, {Src, ShAmt}).getReg(0); in lowerRotate()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 8090 unsigned ShOpc = IsLeft ? ISD::SHL : ISD::SRL; in expandROT() local
8100 ShVal = DAG.getNode(ShOpc, DL, VT, Op0, ShAmt); in expandROT()
8108 ShVal = DAG.getNode(ShOpc, DL, VT, Op0, ShAmt); in expandROT()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 29660 unsigned ShOpc = ConstantAmt ? Opc : X86OpcV; in LowerShift() local
29661 SDValue R0 = DAG.getNode(ShOpc, dl, VT, R, DAG.getBitcast(VT, Amt0)); in LowerShift()
29662 SDValue R1 = DAG.getNode(ShOpc, dl, VT, R, DAG.getBitcast(VT, Amt1)); in LowerShift()
29663 SDValue R2 = DAG.getNode(ShOpc, dl, VT, R, DAG.getBitcast(VT, Amt2)); in LowerShift()
29664 SDValue R3 = DAG.getNode(ShOpc, dl, VT, R, DAG.getBitcast(VT, Amt3)); in LowerShift()
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