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Searched refs:Scl (Results 1 – 10 of 10) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrFMA.td323 SchedWriteFMA.Scl>, VEX_LIG;
325 SchedWriteFMA.Scl>, VEX_LIG;
328 SchedWriteFMA.Scl>, VEX_LIG;
330 SchedWriteFMA.Scl>, VEX_LIG;
542 SchedWriteFMA.Scl>,
543 fma4s_int<0x6A, "vfmaddss", ssmem, SchedWriteFMA.Scl>;
545 SchedWriteFMA.Scl>,
546 fma4s_int<0x6E, "vfmsubss", ssmem, SchedWriteFMA.Scl>;
548 X86any_Fnmadd, loadf32, SchedWriteFMA.Scl>,
549 fma4s_int<0x7A, "vfnmaddss", ssmem, SchedWriteFMA.Scl>;
[all …]
H A DX86InstrAVX512.td1999 SchedWriteFCmp.Scl>, AVX512XSIi8Base;
2003 SchedWriteFCmp.Scl>, AVX512XDIi8Base, REX_W;
2008 SchedWriteFCmp.Scl>, AVX512XSIi8Base, TA;
2593 sched.Scl, f16x_info, HasFP16>,
2602 sched.Scl, f32x_info, HasDQI>, VEX_LIG,
2605 sched.Scl, f64x_info, HasDQI>, VEX_LIG,
5441 sched.PS.Scl, IsCommutable>,
5443 sched.PS.Scl>,
5446 sched.PD.Scl, IsCommutable>,
5448 sched.PD.Scl>,
[all …]
H A DX86InstrXOP.td78 ssmem, sse_load_f32, SchedWriteFRnd.Scl>;
87 sdmem, sse_load_f64, SchedWriteFRnd.Scl>;
H A DX86Schedule.td82 X86FoldableSchedWrite Scl = sScl; // Scalar float/double operations.
118 X86SchedWriteMoveLS Scl = sScl; // Scalar float/double operations.
H A DX86InstrSSE.td1875 SchedWriteFCmpSizes.PS.Scl, sse_load_f32>,
1880 SchedWriteFCmpSizes.PD.Scl, sse_load_f64>,
1887 SchedWriteFCmpSizes.PS.Scl, sse_load_f32>, TB, XS;
1891 SchedWriteFCmpSizes.PD.Scl, sse_load_f64>, TB, XD;
2680 OpNode, FR32, f32mem, SSEPackedSingle, sched.PS.Scl, 0>,
2683 OpNode, FR64, f64mem, SSEPackedDouble, sched.PD.Scl, 0>,
2689 sched.PS.Scl>, TB, XS;
2692 sched.PD.Scl>, TB, XD;
2703 SSEPackedSingle, sched.PS.Scl, 0>, TB, XS, VEX, VVVV, VEX_LIG, WIG;
2706 SSEPackedDouble, sched.PD.Scl, 0>, TB, XD, VEX, VVVV, VEX_LIG, WIG;
[all …]
H A DX86ISelLowering.cpp6007 SDValue Scl = N.getOperand(Opcode == ISD::SCALAR_TO_VECTOR ? 0 : 1); in getFauxShuffleMask() local
6018 if (X86::isZeroNode(Scl)) { in getFauxShuffleMask()
6029 unsigned MinBitsPerElt = Scl.getScalarValueSizeInBits(); in getFauxShuffleMask()
6030 while (Scl.getOpcode() == ISD::TRUNCATE || in getFauxShuffleMask()
6031 Scl.getOpcode() == ISD::ANY_EXTEND || in getFauxShuffleMask()
6032 Scl.getOpcode() == ISD::ZERO_EXTEND || in getFauxShuffleMask()
6033 (Scl.getOpcode() == ISD::BITCAST && in getFauxShuffleMask()
6034 Scl.getScalarValueSizeInBits() == in getFauxShuffleMask()
6035 Scl.getOperand(0).getScalarValueSizeInBits())) { in getFauxShuffleMask()
6036 Scl = Scl.getOperand(0); in getFauxShuffleMask()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMAsmPrinter.cpp157 COFF::SymbolStorageClass Scl = in runOnMachineFunction() local
162 OutStreamer->emitCOFFSymbolStorageClass(Scl); in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64AsmPrinter.cpp183 COFF::SymbolStorageClass Scl = in runOnMachineFunction() local
189 OutStreamer->emitCOFFSymbolStorageClass(Scl); in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp1189 SDValue Scl = Op.getOperand(0); in SimplifyDemandedBits() local
1190 APInt DemandedSclBits = DemandedBits.zextOrTrunc(Scl.getValueSizeInBits()); in SimplifyDemandedBits()
1192 if (SimplifyDemandedBits(Scl, DemandedSclBits, KnownScl, TLO, Depth + 1)) in SimplifyDemandedBits()
1219 SDValue Scl = Op.getOperand(1); in SimplifyDemandedBits() local
1236 unsigned NumSclBits = Scl.getScalarValueSizeInBits(); in SimplifyDemandedBits()
1238 if (SimplifyDemandedBits(Scl, DemandedSclBits, KnownScl, TLO, Depth + 1)) in SimplifyDemandedBits()
3381 SDValue Scl = Op.getOperand(1); in SimplifyDemandedVectorElts() local
3397 KnownUndef.setBitVal(Idx, Scl.isUndef()); in SimplifyDemandedVectorElts()
3399 KnownZero.setBitVal(Idx, isNullConstant(Scl) || isNullFPConstant(Scl)); in SimplifyDemandedVectorElts()
H A DSelectionDAG.cpp2804 SDValue Scl; in isSplatValue() local
2813 if (Scl && Scl != Op) in isSplatValue()
2815 Scl = Op; in isSplatValue()