Searched refs:Scavenged (Results 1 – 4 of 4) sorted by relevance
64 for (ScavengedInfo &SI : Scavenged) { in init() 87 for (ScavengedInfo &I : Scavenged) { in enterBasicBlockEnd() 233 unsigned SI = Scavenged.size(), Diff = std::numeric_limits<unsigned>::max(); in backward() 235 for (unsigned I = 0; I < Scavenged.size(); ++I) { in backward() 236 if (Scavenged[I].Reg != 0) in backward() 239 int FI = Scavenged[I].FrameIndex; in backward() 259 if (SI == Scavenged.size()) { in FindUnusedReg() 262 Scavenged.push_back(ScavengedInfo(FIE)); in FindUnusedReg() 266 Scavenged[SI].Reg = Reg; in getRegsAvailable() 272 int FI = Scavenged[S in getRegsAvailable() 481 ScavengedInfo &Scavenged = spill(Reg, RC, SPAdj, SpillBefore, ReloadBefore); scavengeRegisterBackwards() local [all...]
57 SmallVector<ScavengedInfo, 2> Scavenged;72 for (ScavengedInfo &Slot : Scavenged) {113 Scavenged.push_back(ScavengedInfo(FI));118 for (const ScavengedInfo &SI : Scavenged) in backward() 127 for (const ScavengedInfo &I : Scavenged) in skipTo() 61 SmallVector<ScavengedInfo, 2> Scavenged; global() variable
1346 bool Scavenged = false; in buildSpillLoadStore() local1475 Scavenged = true; in buildSpillLoadStore()1552 SOffsetRegState |= getKillRegState(Scavenged); in buildSpillLoadStore()
301 Register Scavenged = RS->FindUnusedReg(&AArch64::GPR64RegClass); in insertIndirectBranch() local302 if (Scavenged != AArch64::NoRegister && in insertIndirectBranch()304 buildIndirectBranch(Scavenged, NewDestBB); in insertIndirectBranch()305 RS->setRegUsed(Scavenged); in insertIndirectBranch()