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Searched refs:SXTW (Results 1 – 9 of 9) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64AddressingModes.h47 SXTW, enumerator
66 case AArch64_AM::SXTW: return "sxtw"; in getShiftExtendName()
133 case 6: return AArch64_AM::SXTW; in getExtendType()
160 case AArch64_AM::SXTW: return 6; break; in getExtendEncoding()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedPredicates.td24 def CheckExtSXTW : CheckImmOperand_s<3, "AArch64_AM::SXTW">;
44 def CheckMemExtSXTW : CheckImmOperand_s<3, "AArch64_AM::SXTW">;
H A DAArch64RegisterInfo.td1710 // SXTW(8|16|32|64)
1711 def ZPR#RegWidth#AsmOpndExtSXTW8Only : ZPRExtendAsmOperand<"SXTW", RegWidth, 8, 0b1>;
1712 def ZPR#RegWidth#AsmOpndExtSXTW8 : ZPRExtendAsmOperand<"SXTW", RegWidth, 8>;
1713 def ZPR#RegWidth#AsmOpndExtSXTW16 : ZPRExtendAsmOperand<"SXTW", RegWidth, 16>;
1714 def ZPR#RegWidth#AsmOpndExtSXTW32 : ZPRExtendAsmOperand<"SXTW", RegWidth, 32>;
1715 def ZPR#RegWidth#AsmOpndExtSXTW64 : ZPRExtendAsmOperand<"SXTW", RegWidth, 64>;
1717 …def ZPR#RegWidth#ExtSXTW8Only : ZPRExtendRegisterOperand<0b1, 0b0, "SXTW", RegWidth, 8, "On…
1718 def ZPR#RegWidth#ExtSXTW8 : ZPRExtendRegisterOperand<0b1, 0b0, "SXTW", RegWidth, 8>;
1719 def ZPR#RegWidth#ExtSXTW16 : ZPRExtendRegisterOperand<0b1, 0b0, "SXTW", RegWidth, 16>;
1720 def ZPR#RegWidth#ExtSXTW32 : ZPRExtendRegisterOperand<0b1, 0b0, "SXTW", RegWidth, 32>;
[all …]
H A DAArch64FastISel.cpp758 Addr.setExtendType(AArch64_AM::SXTW); in computeAddress()
840 Addr.setExtendType(AArch64_AM::SXTW); in computeAddress()
896 Addr.setExtendType(AArch64_AM::SXTW); in computeAddress()
1073 if (Addr.getExtendType() == AArch64_AM::SXTW || in simplifyAddress()
1086 else if (Addr.getExtendType() == AArch64_AM::SXTW) in simplifyAddress()
1146 bool IsSigned = Addr.getExtendType() == AArch64_AM::SXTW || in addLoadStoreOperands()
1821 Addr.getExtendType() == AArch64_AM::SXTW) in emitLoad()
2111 Addr.getExtendType() == AArch64_AM::SXTW) in emitStore()
3726 AArch64_AM::SXTW, /*ShiftImm=*/0, /*SetFlags=*/true, in fastLowerIntrinsicCall()
H A DAArch64ISelDAGToDAG.cpp823 return AArch64_AM::SXTW; in getExtendTypeForNode()
1221 SignExtend = CurDAG->getTargetConstant(Ext == AArch64_AM::SXTW, dl, in SelectExtendedSHL()
1290 SignExtend = CurDAG->getTargetConstant(Ext == AArch64_AM::SXTW, dl, in SelectAddrModeWRO()
1302 SignExtend = CurDAG->getTargetConstant(Ext == AArch64_AM::SXTW, dl, in SelectAddrModeWRO()
H A DAArch64InstrInfo.cpp3335 if (Extend != AArch64_AM::UXTW && Extend != AArch64_AM::SXTW) in canFoldIntoAddrMode()
3340 (Extend == AArch64_AM::SXTW) ? ExtAddrMode::Formula::SExtScaledReg in canFoldIntoAddrMode()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/
H A DAArch64BaseInfo.h704 SXTW, enumerator
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp1370 ShiftExtendTy == AArch64_AM::SXTW) && in isSVEDataVectorRegWithShiftExtend()
1565 ET == AArch64_AM::UXTW || ET == AArch64_AM::SXTW || in isExtend()
1578 ET == AArch64_AM::UXTW || ET == AArch64_AM::SXTW; in isExtend64()
1610 return (ET == AArch64_AM::UXTW || ET == AArch64_AM::SXTW) && in isMemWExtend()
2246 bool IsSigned = ET == AArch64_AM::SXTW || ET == AArch64_AM::SXTX; in addMemExtendOperands()
2258 bool IsSigned = ET == AArch64_AM::SXTW || ET == AArch64_AM::SXTX; in addMemExtend8Operands()
3666 .Case("sxtw", AArch64_AM::SXTW) in tryParseOptionalShiftExtend()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp7234 case AArch64_AM::SXTW: in isSignExtendShiftType()
7325 if (SignExtend && Ext != AArch64_AM::SXTW) in selectExtendedSHL()
7554 unsigned SignExtend = Ext == AArch64_AM::SXTW; in selectAddrModeWRO()
7781 return AArch64_AM::SXTW; in getExtendTypeForInst()