| /freebsd/contrib/llvm-project/compiler-rt/lib/builtins/hexagon/ |
| H A D | fastmath2_dlib_asm.S | 78 expa = SXTH(manta)
79 expb = SXTH(mantb)
81 expd = SXTH(expd)
179 expa = SXTH(manta)
180 expb = SXTH(mantb)
182 expd = SXTH(expd)
|
| H A D | fastmath_dlib_asm.S | 86 expa = SXTH(manta)
87 expb = SXTH(mantb)
89 expd = SXTH(expd)
221 expa = SXTH(manta)
222 expb = SXTH(mantb)
224 expd = SXTH(expd)
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AddressingModes.h | 46 SXTH, enumerator
65 case AArch64_AM::SXTH: return "sxth"; in getShiftExtendName()
132 case 5: return AArch64_AM::SXTH; in getExtendType()
159 case AArch64_AM::SXTH: return 5; break; in getExtendEncoding()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedPredicates.td | 23 def CheckExtSXTH : CheckImmOperand_s<3, "AArch64_AM::SXTH">;
|
| H A D | AArch64FastISel.cpp | 1177 ExtendType = IsZExt ? AArch64_AM::UXTH : AArch64_AM::SXTH; in emitAddSub()
|
| H A D | AArch64ISelDAGToDAG.cpp | 821 return AArch64_AM::SXTH; in getExtendTypeForNode()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.h | 703 SXTH, enumerator
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 302 STORE_OPCODE(SEXT16, SXTH); in OpcodeCache()
|
| H A D | ARMFastISel.cpp | 2731 /* 16 bit sext */ { { ARM::SXTH , 0, ARM_AM::no_shift, 0 }, in ARMEmitIntExt()
2975 { { ARM::SXTH, ARM::t2SXTH }, 0, 0, MVT::i16 },
|
| H A D | ARMScheduleR52.td | 215 (instregex "SXTB", "SXTH", "SXTB16", "UXTB", "UXTH", "UXTB16",
|
| H A D | ARMScheduleSwift.td | 161 (instregex "SXTB", "SXTH", "SXTB16", "UXTB", "UXTH", "UXTB16",
|
| H A D | ARMScheduleA57.td | 360 // Sign/zero extend, normal: SXTB, SXTH, UXTB, UXTH
|
| H A D | ARMInstrInfo.td | 3773 def SXTH : AI_ext_rrot<0b01101011,
6204 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
6326 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
|
| H A D | ARMInstrThumb2.td | 2357 // SXTH operations with a rotate of 24: there the non-contiguous bits are
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 1564 ET == AArch64_AM::UXTH || ET == AArch64_AM::SXTH || in isExtend()
1577 ET == AArch64_AM::UXTH || ET == AArch64_AM::SXTH || in isExtend64()
3665 .Case("sxth", AArch64_AM::SXTH) in tryParseOptionalShiftExtend()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 7233 case AArch64_AM::SXTH: in isSignExtendShiftType()
7779 return IsLoadStore ? AArch64_AM::InvalidShiftExtend : AArch64_AM::SXTH; in getExtendTypeForInst()
|