Searched refs:SVEDataVector (Results 1 – 2 of 2) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 70 SVEDataVector, enumerator
1265 RK = RegKind::SVEDataVector; in isSVEVectorReg()
1326 if (Kind != k_Register || Reg.Kind != RegKind::SVEDataVector) in isSVEDataVectorRegOfWidth()
2287 assert((Kind == RegKind::NeonVector || Kind == RegKind::SVEDataVector || in CreateVectorReg()
2711 case RegKind::SVEDataVector: in parseVectorKind()
2952 return Kind == RegKind::SVEDataVector ? RegNum : 0; in matchRegisterNameAlias()
3001 case RegKind::SVEDataVector: in getNumRegsForRegKind()
7226 RegisterKind = RegKind::SVEDataVector; in parseDirectiveReq()
7228 tryParseVectorRegister(RegNum, Kind, RegKind::SVEDataVector); in parseDirectiveReq()
7943 tryParseVectorRegister(RegNum, Kind, RegKind::SVEDataVector); in tryParseSVEDataVector()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterInfo.td | 1232 let ParserMethod = "tryParseVectorList<RegKind::SVEDataVector>";
1234 "isTypedVectorList<RegKind::SVEDataVector, " #NumRegs #", 0, " #ElementWidth #">";
1331 "isTypedVectorListMultiple<RegKind::SVEDataVector, " # NumRegs # ", 0, "
1443 let PredicateMethod = "isTypedVectorListStrided<RegKind::SVEDataVector, "
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