Searched refs:SV0 (Results 1 – 3 of 3) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineSelect.cpp | 2503 Value *SV0, *SV1, *SA0, *SA1; in foldSelectFunnelShift() local
2504 if (!match(Or0, m_OneUse(m_LogicalShift(m_Value(SV0), in foldSelectFunnelShift()
2514 std::swap(SV0, SV1); in foldSelectFunnelShift()
2536 if ((IsFshl && TVal != SV0) || (!IsFshl && TVal != SV1)) in foldSelectFunnelShift()
2547 if (SV0 != SV1) { in foldSelectFunnelShift()
2550 else if (!IsFshl && !llvm::isGuaranteedNotToBePoison(SV0)) in foldSelectFunnelShift()
2551 SV0 = Builder.CreateFreeze(SV0); in foldSelectFunnelShift()
2560 return CallInst::Create(F, { SV0, SV1, ShAmt }); in foldSelectFunnelShift()
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| /freebsd/sys/contrib/device-tree/Bindings/sound/ |
| H A D | renesas,rsnd.txt | 129 amixer set "CTU SV0" 0,4194304
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 3167 const APInt &SV0 = N0.getOperand(1)->getConstantOperandAPInt(0); in visitADD() local
3169 APInt NewStep = SV0 + SV1; in visitADD()
8331 auto *SV0 = dyn_cast<ShuffleVectorSDNode>(N0); in visitOR() local
8333 if (SV0 && SV1 && TLI.isTypeLegal(VT)) { in visitOR()
8347 int M0 = SV0->getMaskElt(i); in visitOR()
16679 SDValue SV0 = PeekThroughBitcast(N0->getOperand(0)); in visitBITCAST() local
16681 if (!(SV0 && SV1)) in visitBITCAST()
16692 TLI.buildLegalVectorShuffle(VT, SDLoc(N), SV0, SV1, NewMask, DAG); in visitBITCAST()
25021 SDValue SV0 = DAG.getUNDEF(VT), SV1 = DAG.getUNDEF(VT); in combineConcatVectorOfExtracts() local
25066 if (SV0.isUndef() || SV0 == ExtVec) { in combineConcatVectorOfExtracts()
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