| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 290 SUBC, enumerator
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 112 SUBC, // Sub with carry enumerator
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| H A D | ARMISelLowering.cpp | 1734 MAKE_CASE(ARMISD::SUBC) in getTargetNodeName()
5088 SDValue Carry = DAG.getNode(ARMISD::SUBC, DL, in ConvertBooleanCarryToCarryFlag()
5128 Value = DAG.getNode(ARMISD::SUBC, dl, VTs, LHS, RHS); in LowerUnsignedALUO()
13007 AddcSubcNode->getOpcode() != ARMISD::SUBC)) in AddCombineTo64bitMLAL()
13105 if (AddcSubcNode->getOpcode() == ARMISD::SUBC) { in AddCombineTo64bitMLAL()
13114 } else if (AddcSubcNode->getOpcode() == ARMISD::SUBC) in AddCombineTo64bitMLAL()
13219 if (N->getOpcode() == ARMISD::SUBC && N->hasAnyUseOfValue(1)) { in PerformAddcSubcCombine()
13237 unsigned Opcode = (N->getOpcode() == ARMISD::ADDC) ? ARMISD::SUBC in PerformAddcSubcCombine()
18569 DAG.getNode(ARMISD::SUBC, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS); in PerformCMOVCombine()
18581 DAG.getNode(ARMISD::SUBC, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS); in PerformCMOVCombine()
[all …]
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| H A D | ARMISelDAGToDAG.cpp | 3973 N->getOperand(2).getOpcode() != ARMISD::SUBC || in Select()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.h | 40 SUBC, // Sub with carry: (X, Y, Cin) -> (X+~Y+Cin, Cout). enumerator
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| H A D | HexagonISelLowering.cpp | 1931 case HexagonISD::SUBC: return "HexagonISD::SUBC"; in getTargetNodeName()
3327 SDValue SubC = DAG.getNode(HexagonISD::SUBC, dl, Op.getNode()->getVTList(), in LowerUAddSubOCarry()
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| H A D | HexagonISelDAGToDAG.cpp | 1042 case HexagonISD::SUBC: return SelectAddSubCarry(N); in Select()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCISelLowering.cpp | 127 setOperationAction(ISD::SUBC, MVT::i32, Legal); in ARCTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 366 case ISD::SUBC: return "subc"; in getOperationName()
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| H A D | LegalizeIntegerTypes.cpp | 3062 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break; in ExpandIntegerResult()
3614 ISD::ADDC : ISD::SUBC, in ExpandIntRes_ADDSUB()
3624 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps); in ExpandIntRes_ADDSUB()
3733 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps); in ExpandIntRes_ADDSUBC()
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| H A D | SelectionDAG.cpp | 4138 case ISD::SUBC: { in computeKnownBits()
5580 case ISD::SUBC: in canCreateUndefOrPoison()
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| H A D | TargetLowering.cpp | 5547 if (auto *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) in SimplifySetCC() local
5551 DAG.getConstant(SUBC->getAPIntValue() - RHSC->getAPIntValue(), in SimplifySetCC()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.h | 167 SUBC, enumerator
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 112 setOperationAction(ISD::SUBC, VT, Custom); in M68kTargetLowering()
1401 case ISD::SUBC: in LowerOperation()
2630 case ISD::SUBC: in LowerADDC_ADDE_SUBC_SUBE()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 631 case ISD::SUBC: in Select()
967 ConsumeCarry || Opcode == ISD::ADDC || Opcode == ISD::SUBC; in SelectADD_SUB_I64()
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| H A D | R600ISelLowering.cpp | 192 setOperationAction({ISD::ADDC, ISD::SUBC, ISD::ADDE, ISD::SUBE}, VT, in R600TargetLowering()
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| H A D | AMDGPUISelLowering.cpp | 488 setOperationAction({ISD::ADDC, ISD::SUBC, ISD::ADDE, ISD::SUBE}, VT, Legal); in AMDGPUTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 833 setOperationAction({ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}, VT, in initActions()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 649 ISD::SSUBO_CARRY, ISD::SSUBSAT, ISD::SUB, ISD::SUBC, in NVPTXTargetLowering()
819 setOperationAction(ISD::SUBC, MVT::i32, Legal); in NVPTXTargetLowering()
824 setOperationAction(ISD::SUBC, MVT::i64, Legal); in NVPTXTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430InstrInfo.td | 534 defm SUBC : Arith<0b0111, "subc", sube, 0, [SR]>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 72 setOperationAction(ISD::SUBC, VT, Legal); in AVRTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 450 def subc : SDNode<"ISD::SUBC" , SDTIntBinOp,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcInstrInfo.td | 895 defm SUBC : F3_12np <"subx", 0b001100>;
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| H A D | SparcISelLowering.cpp | 1729 setOperationAction(ISD::SUBC, MVT::i32, Legal); in SparcTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 161 ISD::SRL_PARTS, ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}) { in WebAssemblyTargetLowering()
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