| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 277 SUBC, enumerator
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 110 SUBC, // Sub with carry enumerator
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| H A D | ARMISelLowering.cpp | 1739 MAKE_CASE(ARMISD::SUBC) in getTargetNodeName()
5025 SDValue Carry = DAG.getNode(ARMISD::SUBC, DL, in ConvertBooleanCarryToCarryFlag()
5065 Value = DAG.getNode(ARMISD::SUBC, dl, VTs, LHS, RHS); in LowerUnsignedALUO()
12940 AddcSubcNode->getOpcode() != ARMISD::SUBC)) in AddCombineTo64bitMLAL()
13038 if (AddcSubcNode->getOpcode() == ARMISD::SUBC) { in AddCombineTo64bitMLAL()
13047 } else if (AddcSubcNode->getOpcode() == ARMISD::SUBC) in AddCombineTo64bitMLAL()
13152 if (N->getOpcode() == ARMISD::SUBC && N->hasAnyUseOfValue(1)) { in PerformAddcSubcCombine()
13170 unsigned Opcode = (N->getOpcode() == ARMISD::ADDC) ? ARMISD::SUBC in PerformAddcSubcCombine()
18496 DAG.getNode(ARMISD::SUBC, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS); in PerformCMOVCombine()
18510 DAG.getNode(ARMISD::SUBC, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS); in PerformCMOVCombine()
[all …]
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| H A D | ARMISelDAGToDAG.cpp | 3979 N->getOperand(2).getOpcode() != ARMISD::SUBC || in Select()
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| H A D | ARMInstrInfo.td | 200 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.h | 40 SUBC, // Sub with carry: (X, Y, Cin) -> (X+~Y+Cin, Cout). enumerator
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| H A D | HexagonISelLowering.cpp | 1909 case HexagonISD::SUBC: return "HexagonISD::SUBC"; in getTargetNodeName()
3305 SDValue SubC = DAG.getNode(HexagonISD::SUBC, dl, Op.getNode()->getVTList(), in LowerUAddSubOCarry()
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| H A D | HexagonISelDAGToDAG.cpp | 1041 case HexagonISD::SUBC: return SelectAddSubCarry(N); in Select()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCISelLowering.cpp | 126 setOperationAction(ISD::SUBC, MVT::i32, Legal); in ARCTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 349 case ISD::SUBC: return "subc"; in getOperationName()
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| H A D | LegalizeIntegerTypes.cpp | 2879 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break; in ExpandIntegerResult()
3417 ISD::ADDC : ISD::SUBC, in ExpandIntRes_ADDSUB()
3427 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps); in ExpandIntRes_ADDSUB()
3535 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps); in ExpandIntRes_ADDSUBC()
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| H A D | TargetLowering.cpp | 5333 if (auto *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) in SimplifySetCC() local
5337 DAG.getConstant(SUBC->getAPIntValue() - RHSC->getAPIntValue(), in SimplifySetCC()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1736 setOperationAction(ISD::SUBC, MVT::i32, Custom); in SparcTargetLowering()
1742 setOperationAction(ISD::SUBC, MVT::i64, Custom); in SparcTargetLowering()
3133 case ISD::SUBC: hiOpc = ISD::SUBE; break; in LowerADDC_ADDE_SUBC_SUBE()
3288 case ISD::SUBC: in LowerOperation()
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| H A D | SparcInstrInfo.td | 847 defm SUBC : F3_12np <"subx", 0b001100>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 110 setOperationAction(ISD::SUBC, VT, Custom); in M68kTargetLowering()
1399 case ISD::SUBC: in LowerOperation()
2629 case ISD::SUBC: in LowerADDC_ADDE_SUBC_SUBE()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 519 case ISD::SUBC: in Select()
851 ConsumeCarry || Opcode == ISD::ADDC || Opcode == ISD::SUBC; in SelectADD_SUB_I64()
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| H A D | R600ISelLowering.cpp | 188 setOperationAction({ISD::ADDC, ISD::SUBC, ISD::ADDE, ISD::SUBE}, VT, in R600TargetLowering()
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| H A D | AMDGPUISelLowering.cpp | 475 setOperationAction({ISD::ADDC, ISD::SUBC, ISD::ADDE, ISD::SUBE}, VT, Legal); in AMDGPUTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 742 setOperationAction({ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}, VT, in initActions()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 538 ISD::SSUBO_CARRY, ISD::SSUBSAT, ISD::SUB, ISD::SUBC, in NVPTXTargetLowering()
709 setOperationAction(ISD::SUBC, MVT::i32, Legal); in NVPTXTargetLowering()
714 setOperationAction(ISD::SUBC, MVT::i64, Legal); in NVPTXTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430InstrInfo.td | 550 defm SUBC : Arith<0b0111, "subc", sube, 0, [SR]>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 73 setOperationAction(ISD::SUBC, VT, Legal); in AVRTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 158 ISD::SRL_PARTS, ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}) { in WebAssemblyTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 434 def subc : SDNode<"ISD::SUBC" , SDTIntBinOp,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 255 setOperationAction(ISD::SUBC, VT, Legal); in PPCTargetLowering()
17914 SDValue Subc = DAG.getNode(ISD::SUBC, DL, DAG.getVTList(MVT::i64, MVT::Glue), in combineADDToADDZE()
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