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Searched refs:SU (Results 1 – 25 of 124) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DVLIWMachineScheduler.cpp108 bool VLIWResourceModel::isResourceAvailable(SUnit *SU, bool IsTop) { in isResourceAvailable() argument
109 if (!SU || !SU->getInstr()) in isResourceAvailable()
114 switch (SU->getInstr()->getOpcode()) { in isResourceAvailable()
116 if (!ResourcesModel->canReserveResources(*SU->getInstr())) in isResourceAvailable()
134 if (hasDependence(U, SU)) in isResourceAvailable()
138 if (hasDependence(SU, U)) in isResourceAvailable()
145 bool VLIWResourceModel::reserveResources(SUnit *SU, bool IsTop) { in reserveResources() argument
148 if (!SU) { in reserveResources()
155 if (!isResourceAvailable(SU, IsTop) || in reserveResources()
162 switch (SU->getInstr()->getOpcode()) { in reserveResources()
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H A DScheduleDAGInstrs.cpp104 for (const SUnit *SU : L) { in dumpSUList() local
105 dbgs() << "SU(" << SU->NodeNum << ")"; in dumpSUList()
106 if (SU != L.back()) in dumpSUList()
238 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) { in addPhysRegDataDeps() argument
239 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx); in addPhysRegDataDeps()
248 const MCInstrDesc &DefMIDesc = SU->getInstr()->getDesc(); in addPhysRegDataDeps()
254 SUnit *UseSU = I->SU; in addPhysRegDataDeps()
255 if (UseSU == SU) in addPhysRegDataDeps()
265 Dep = SDep(SU, SDep::Artificial); in addPhysRegDataDeps()
269 SU->hasPhysRegDefs = true; in addPhysRegDataDeps()
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H A DMachineScheduler.cpp687 for (const SUnit *SU : Queue) in dump() local
688 dbgs() << SU->NodeNum << " "; in dump()
706 void ScheduleDAGMI::releaseSucc(SUnit *SU, SDep *SuccEdge) { in releaseSucc() argument
725 if (SuccSU->TopReadyCycle < SU->TopReadyCycle + SuccEdge->getLatency()) in releaseSucc()
726 SuccSU->TopReadyCycle = SU->TopReadyCycle + SuccEdge->getLatency(); in releaseSucc()
734 void ScheduleDAGMI::releaseSuccessors(SUnit *SU) { in releaseSuccessors() argument
735 for (SDep &Succ : SU->Succs) in releaseSuccessors()
736 releaseSucc(SU, &Succ); in releaseSuccessors()
743 void ScheduleDAGMI::releasePred(SUnit *SU, SDep *PredEdge) { in releasePred() argument
762 if (PredSU->BotReadyCycle < SU->BotReadyCycle + PredEdge->getLatency()) in releasePred()
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H A DScheduleDAG.cpp223 SUnit *SU = WorkList.pop_back_val(); in setDepthDirty() local
224 SU->isDepthCurrent = false; in setDepthDirty()
225 for (SDep &SuccDep : SU->Succs) { in setDepthDirty()
238 SUnit *SU = WorkList.pop_back_val(); in setHeightDirty() local
239 SU->isHeightCurrent = false; in setHeightDirty()
240 for (SDep &PredDep : SU->Preds) { in setHeightDirty()
357 LLVM_DUMP_METHOD void ScheduleDAG::dumpNodeName(const SUnit &SU) const { in dumpNodeName()
358 if (&SU == &EntrySU) in dumpNodeName()
360 else if (&SU == &ExitSU) in dumpNodeName()
363 dbgs() << "SU(" << SU.NodeNum << ")"; in dumpNodeName()
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H A DLatencyPriorityQueue.cpp56 SUnit *LatencyPriorityQueue::getSingleUnscheduledPred(SUnit *SU) { in getSingleUnscheduledPred() argument
58 for (const SDep &P : SU->Preds) { in getSingleUnscheduledPred()
72 void LatencyPriorityQueue::push(SUnit *SU) { in push() argument
76 for (const SDep &Succ : SU->Succs) in push()
77 if (getSingleUnscheduledPred(Succ.getSUnit()) == SU) in push()
79 NumNodesSolelyBlocking[SU->NodeNum] = NumNodesBlocking; in push()
81 Queue.push_back(SU); in push()
89 void LatencyPriorityQueue::scheduledNode(SUnit *SU) { in scheduledNode() argument
90 for (const SDep &Succ : SU->Succs) in scheduledNode()
100 void LatencyPriorityQueue::AdjustPriorityOfUnscheduledPreds(SUnit *SU) { in AdjustPriorityOfUnscheduledPreds() argument
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H A DMacroFusion.cpp38 static SUnit *getPredClusterSU(const SUnit &SU) { in getPredClusterSU() argument
39 for (const SDep &SI : SU.Preds) in getPredClusterSU()
46 bool llvm::hasLessThanNumFused(const SUnit &SU, unsigned FuseLimit) { in hasLessThanNumFused() argument
48 const SUnit *CurrentSU = &SU; in hasLessThanNumFused()
100 SUnit *SU = SI.getSUnit(); in fuseInstructionPair() local
102 SU == &DAG.ExitSU || SU == &SecondSU || SU->isPred(&SecondSU)) in fuseInstructionPair()
105 dbgs() << " - "; DAG.dumpNodeName(*SU); dbgs() << '\n';); in fuseInstructionPair()
106 DAG.addEdge(SU, SDe in fuseInstructionPair()
113 SUnit *SU = SI.getSUnit(); fuseInstructionPair() local
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DResourcePriorityQueue.cpp67 ResourcePriorityQueue::numberRCValPredInSU(SUnit *SU, unsigned RCId) { in numberRCValPredInSU() argument
69 for (SDep &Pred : SU->Preds) { in numberRCValPredInSU()
104 unsigned ResourcePriorityQueue::numberRCValSuccInSU(SUnit *SU, in numberRCValSuccInSU() argument
107 for (const SDep &Succ : SU->Succs) { in numberRCValSuccInSU()
142 static unsigned numberCtrlDepsInSU(SUnit *SU) { in numberCtrlDepsInSU() argument
144 for (const SDep &Succ : SU->Succs) in numberCtrlDepsInSU()
151 static unsigned numberCtrlPredInSU(SUnit *SU) { in numberCtrlPredInSU() argument
153 for (SDep &Pred : SU->Preds) in numberCtrlPredInSU()
167 for (SUnit &SU : *SUnits) { in initNodes()
168 initNumRegDefsLeft(&SU); in initNodes()
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H A DScheduleDAGRRList.cpp211 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) { in IsReachable() argument
212 return Topo.IsReachable(SU, TargetSU); in IsReachable()
217 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) { in WillCreateCycle() argument
218 return Topo.WillCreateCycle(SU, TargetSU); in WillCreateCycle()
224 void AddPredQueued(SUnit *SU, const SDep &D) { in AddPredQueued() argument
225 Topo.AddPredQueued(SU, D.getSUnit()); in AddPredQueued()
226 SU->addPred(D); in AddPredQueued()
232 void AddPred(SUnit *SU, const SDep &D) { in AddPred() argument
233 Topo.AddPred(SU, D.getSUnit()); in AddPred()
234 SU->addPred(D); in AddPred()
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H A DScheduleDAGVLIW.cpp81 void releaseSucc(SUnit *SU, const SDep &D);
82 void releaseSuccessors(SUnit *SU);
83 void scheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
109 void ScheduleDAGVLIW::releaseSucc(SUnit *SU, const SDep &D) { in releaseSucc() argument
124 SuccSU->setDepthToAtLeast(SU->getDepth() + D.getLatency()); in releaseSucc()
133 void ScheduleDAGVLIW::releaseSuccessors(SUnit *SU) { in releaseSuccessors() argument
135 for (SDep &Succ : SU->Succs) { in releaseSuccessors()
139 releaseSucc(SU, Succ); in releaseSuccessors()
146 void ScheduleDAGVLIW::scheduleNodeTopDown(SUnit *SU, unsigned CurCycle) { in scheduleNodeTopDown() argument
148 LLVM_DEBUG(dumpNode(*SU)); in scheduleNodeTopDown()
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H A DScheduleDAGFast.cpp84 void AddPred(SUnit *SU, const SDep &D) { in AddPred() argument
85 SU->addPred(D); in AddPred()
90 void RemovePred(SUnit *SU, const SDep &D) { in RemovePred() argument
91 SU->removePred(D); in RemovePred()
95 void ReleasePred(SUnit *SU, SDep *PredEdge);
96 void ReleasePredecessors(SUnit *SU, unsigned CurCycle);
135 void ScheduleDAGFast::ReleasePred(SUnit *SU, SDep *PredEdge) { in ReleasePred() argument
156 void ScheduleDAGFast::ReleasePredecessors(SUnit *SU, unsigned CurCycle) { in ReleasePredecessors() argument
158 for (SDep &Pred : SU->Preds) { in ReleasePredecessors()
159 ReleasePred(SU, &Pred); in ReleasePredecessors()
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H A DScheduleDAGSDNodes.cpp79 SUnit *SU = &SUnits.back(); in newSUnit() local
84 SU->SchedulingPref = Sched::None; in newSUnit()
86 SU->SchedulingPref = TLI.getSchedulingPreference(N); in newSUnit()
87 return SU; in newSUnit()
91 SUnit *SU = newSUnit(Old->getNode()); in Clone() local
92 SU->OrigNode = Old->OrigNode; in Clone()
93 SU->Latency = Old->Latency; in Clone()
94 SU->isVRegCycle = Old->isVRegCycle; in Clone()
95 SU->isCall = Old->isCall; in Clone()
96 SU->isCallOp = Old->isCallOp; in Clone()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNMinRegStrategy.cpp25 const SUnit *SU; member
29 : SU(SU_), Priority(Priority_) {} in Candidate()
38 bool isScheduled(const SUnit *SU) const { in isScheduled()
39 assert(!SU->isBoundaryNode()); in isScheduled()
40 return NumPreds[SU->NodeNum] == std::numeric_limits<unsigned>::max(); in isScheduled()
43 void setIsScheduled(const SUnit *SU) { in setIsScheduled() argument
44 assert(!SU->isBoundaryNode()); in setIsScheduled()
45 NumPreds[SU->NodeNum] = std::numeric_limits<unsigned>::max(); in setIsScheduled()
48 unsigned getNumPreds(const SUnit *SU) const { in getNumPreds()
49 assert(!SU->isBoundaryNode()); in getNumPreds()
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H A DGCNILPSched.cpp23 SUnit *SU; member
26 : SU(SU_) {} in Candidate()
40 unsigned getNodePriority(const SUnit *SU) const;
47 void releasePredecessors(const SUnit* SU);
58 CalcNodeSethiUllmanNumber(const SUnit *SU, std::vector<unsigned> &SUNumbers) { in CalcNodeSethiUllmanNumber() argument
59 unsigned &SethiUllmanNumber = SUNumbers[SU->NodeNum]; in CalcNodeSethiUllmanNumber()
64 for (const SDep &Pred : SU->Preds) { in CalcNodeSethiUllmanNumber()
86 unsigned GCNILPScheduler::getNodePriority(const SUnit *SU) const { in getNodePriority()
87 assert(SU->NodeNum < SUNumbers.size()); in getNodePriority()
88 if (SU->NumSuccs == 0 && SU->NumPreds != 0) in getNodePriority()
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H A DR600MachineScheduler.cpp53 SUnit *SU = nullptr; in pickNode() local
93 if (!SU && ((AllowSwitchToAlu && CurInstKind != IDAlu) || in pickNode()
96 SU = pickAlu(); in pickNode()
97 if (!SU && !PhysicalRegCopy.empty()) { in pickNode()
98 SU = PhysicalRegCopy.front(); in pickNode()
101 if (SU) { in pickNode()
108 if (!SU) { in pickNode()
110 SU = pickOther(IDFetch); in pickNode()
111 if (SU) in pickNode()
116 if (!SU) { in pickNode()
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H A DSIMachineScheduler.cpp176 void SIScheduleBlock::addUnit(SUnit *SU) { in addUnit() argument
177 NodeNum2Index[SU->NodeNum] = SUnits.size(); in addUnit()
178 SUnits.push_back(SU); in addUnit()
184 dbgs() << " SU(" << Cand.SU->NodeNum << ") " << getReasonStr(Cand.Reason); in traceCandidate()
236 if (TryCand.SU->NodeNum < Cand.SU->NodeNum) { in tryCandidateTopDown()
244 for (SUnit* SU : TopReadySUs) { in pickNode()
249 TryCand.SU = SU; in pickNode()
250 TopRPTracker.getDownwardPressure(SU->getInstr(), pressure, MaxPressure); in pickNode()
253 TryCand.IsLowLatency = DAG->IsLowLatencySU[SU->NodeNum]; in pickNode()
254 TryCand.LowLatencyOffset = DAG->LowLatencyOffset[SU->NodeNum]; in pickNode()
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H A DAMDGPUExportClustering.cpp29 static bool isExport(const SUnit &SU) { in isExport() argument
30 return SIInstrInfo::isEXP(*SU.getInstr()); in isExport()
33 static bool isPositionExport(const SIInstrInfo *TII, SUnit *SU) { in isPositionExport() argument
34 const MachineInstr *MI = SU->getInstr(); in isPositionExport()
51 for (SUnit *SU : Copy) { in sortChain()
52 if (isPositionExport(TII, SU)) in sortChain()
53 Chain[PosIdx++] = SU; in sortChain()
55 Chain[OtherIdx++] = SU; in sortChain()
82 static void removeExportDependencies(ScheduleDAGInstrs *DAG, SUnit &SU) { in removeExportDependencies() argument
85 for (const SDep &Pred : SU.Preds) { in removeExportDependencies()
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZHazardRecognizer.cpp46 getNumDecoderSlots(SUnit *SU) const { in getNumDecoderSlots()
47 const MCSchedClassDesc *SC = getSchedClass(SU); in getNumDecoderSlots()
61 unsigned SystemZHazardRecognizer::getCurrCycleIdx(SUnit *SU) const { in getCurrCycleIdx()
66 if (SU != nullptr && !fitsIntoCurrentGroup(SU)) { in getCurrCycleIdx()
77 getHazardType(SUnit *SU, int Stalls) { in getHazardType() argument
78 return (fitsIntoCurrentGroup(SU) ? NoHazard : Hazard); in getHazardType()
92 SystemZHazardRecognizer::fitsIntoCurrentGroup(SUnit *SU) const { in fitsIntoCurrentGroup()
93 const MCSchedClassDesc *SC = getSchedClass(SU); in fitsIntoCurrentGroup()
105 if (CurrGroupSize == 2 && has4RegOps(SU in fitsIntoCurrentGroup()
167 dumpSU(SUnit * SU,raw_ostream & OS) const dumpSU() argument
271 EmitInstruction(SUnit * SU) EmitInstruction() argument
387 resourcesCost(SUnit * SU) resourcesCost() argument
413 SUnit SU(MI, 0); emitInstruction() local
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H A DSystemZMachineScheduler.cpp29 for (auto &SU : *this) { in dump()
30 HazardRec.dumpSU(SU, dbgs()); in dump()
31 if (SU != *rbegin()) in dump()
176 for (auto *SU : Available) { in pickNode() local
179 Candidate c(SU, *HazardRec); in pickNode()
182 if (Best.SU == nullptr || c < Best) { in pickNode()
187 LLVM_DEBUG(HazardRec->dumpSU(c.SU, dbgs()); c.dumpCosts(); in pickNode()
188 dbgs() << " Height:" << c.SU->getHeight(); dbgs() << "\n";); in pickNode()
192 if (!SU->isScheduleHigh && Best.noCost()) in pickNode()
196 assert (Best.SU != nullptr); in pickNode()
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H A DSystemZHazardRecognizer.h72 inline unsigned getNumDecoderSlots(SUnit *SU) const;
75 bool fitsIntoCurrentGroup(SUnit *SU) const;
85 unsigned getCurrCycleIdx(SUnit *SU = nullptr) const;
104 bool isFPdOpPreferred_distance(SUnit *SU) const;
116 HazardType getHazardType(SUnit *SU, int Stalls = 0) override;
118 void EmitInstruction(SUnit *SU) override;
121 const MCSchedClassDesc *getSchedClass(SUnit *SU) const { in getSchedClass() argument
122 if (!SU->SchedClass && SchedModel->hasInstrSchedModel()) in getSchedClass()
123 SU->SchedClass = SchedModel->resolveSchedClass(SU->getInstr()); in getSchedClass()
124 return SU->SchedClass; in getSchedClass()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineScheduler.h261 virtual void schedNode(SUnit *SU, bool IsTopNode) = 0;
265 virtual void releaseTopNode(SUnit *SU) = 0;
269 virtual void releaseBottomNode(SUnit *SU) = 0;
373 void updateQueues(SUnit *SU, bool IsTopNode);
390 void releaseSucc(SUnit *SU, SDep *SuccEdge);
391 void releaseSuccessors(SUnit *SU);
392 void releasePred(SUnit *SU, SDep *PredEdge);
393 void releasePredecessors(SUnit *SU);
466 PressureDiff &getPressureDiff(const SUnit *SU) { in getPressureDiff() argument
467 return SUPressureDiffs[SU->NodeNum]; in getPressureDiff()
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H A DScheduleDAGInstrs.h55 SUnit *SU; member
57 VReg2SUnit(unsigned VReg, LaneBitmask LaneMask, SUnit *SU) in VReg2SUnit()
58 : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {} in VReg2SUnit()
70 unsigned OperandIndex, SUnit *SU) in VReg2SUnitOperIdx()
71 : VReg2SUnit(VReg, LaneMask, SU), OperandIndex(OperandIndex) {} in VReg2SUnitOperIdx()
77 SUnit *SU; member
82 : SU(su), OpIdx(op), RegUnit(R) {} in PhysRegSUOper()
217 void addChainDependencies(SUnit *SU, SUList &SUs, unsigned Latency) { in addChainDependencies() argument
219 addChainDependency(SU, Entry, Latency); in addChainDependencies()
223 void addChainDependencies(SUnit *SU, Value2SUsMap &Val2SUsMap);
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H A DVLIWMachineScheduler.h58 virtual bool isResourceAvailable(SUnit *SU, bool IsTop);
59 virtual bool reserveResources(SUnit *SU, bool IsTop);
62 bool isInPacket(SUnit *SU) const { return is_contained(Packet, SU); } in isInPacket() argument
95 SUnit *SU = nullptr; member
179 for (auto &SU : DAG->SUnits) in init()
180 MaxPath = std::max(MaxPath, isTop() ? SU.getHeight() : SU.getDepth()); in init()
189 bool checkHazard(SUnit *SU);
191 void releaseNode(SUnit *SU, unsigne
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H A DResourcePriorityQueue.h83 void addNode(const SUnit *SU) override { in addNode() argument
87 void updateNode(const SUnit *SU) override {} in updateNode() argument
105 int SUSchedulingCost (SUnit *SU);
109 void initNumRegDefsLeft(SUnit *SU);
110 int regPressureDelta(SUnit *SU, bool RawPressure = false);
111 int rawRegPressureDelta (SUnit *SU, unsigned RCId);
119 void remove(SUnit *SU) override;
122 void scheduledNode(SUnit *SU) override;
123 bool isResourceAvailable(SUnit *SU);
124 void reserveResources(SUnit *SU);
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCHazardRecognizers.cpp24 bool PPCDispatchGroupSBHazardRecognizer::isLoadAfterStore(SUnit *SU) { in isLoadAfterStore() argument
26 if (isBCTRAfterSet(SU)) in isLoadAfterStore()
29 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in isLoadAfterStore()
38 for (unsigned i = 0, ie = (unsigned) SU->Preds.size(); i != ie; ++i) { in isLoadAfterStore()
39 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit()); in isLoadAfterStore()
43 if (!SU->Preds[i].isNormalMemory() && !SU->Preds[i].isBarrier()) in isLoadAfterStore()
47 if (SU->Preds[i].getSUnit() == CurGroup[j]) in isLoadAfterStore()
54 bool PPCDispatchGroupSBHazardRecognizer::isBCTRAfterSet(SUnit *SU) { in isBCTRAfterSet() argument
55 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in isBCTRAfterSet()
64 for (unsigned i = 0, ie = (unsigned) SU->Preds.size(); i != ie; ++i) { in isBCTRAfterSet()
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H A DPPCMachineScheduler.cpp25 return Cand.SU->getInstr()->getOpcode() == PPC::ADDI || in isADDIInstr()
26 Cand.SU->getInstr()->getOpcode() == PPC::ADDI8; in isADDIInstr()
37 if (isADDIInstr(FirstCand) && SecondCand.SU->getInstr()->mayLoad()) { in biasAddiLoadCandidate()
41 if (FirstCand.SU->getInstr()->mayLoad() && isADDIInstr(SecondCand)) { in biasAddiLoadCandidate()
61 if (tryGreater(biasPhysReg(TryCand.SU, TryCand.AtTop), in tryCandidate()
62 biasPhysReg(Cand.SU, Cand.AtTop), TryCand, Cand, PhysReg)) in tryCandidate()
92 if (tryLess(Zone->getLatencyStallCycles(TryCand.SU), in tryCandidate()
93 Zone->getLatencyStallCycles(Cand.SU), TryCand, Cand, Stall)) in tryCandidate()
107 if (tryGreater(TryCand.SU == TryCandNextClusterSU, in tryCandidate()
108 Cand.SU == CandNextClusterSU, TryCand, Cand, Cluster)) in tryCandidate()
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