| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 505 STRICT_FSETCCS, enumerator
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| H A D | SelectionDAG.h | 1319 return getNode(IsSignaling ? ISD::STRICT_FSETCCS : ISD::STRICT_FSETCC, DL,
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorOps.cpp | 329 Op.getOpcode() == ISD::STRICT_FSETCCS) { in LegalizeOp()
2027 Node->getOpcode() == ISD::STRICT_FSETCCS; in ExpandSETCC()
2028 bool IsSignaling = Node->getOpcode() == ISD::STRICT_FSETCCS; in ExpandSETCC()
2148 Node->getOpcode() == ISD::STRICT_FSETCCS) { in ExpandStrictFPOp()
2288 Node->getOpcode() == ISD::STRICT_FSETCCS) in UnrollStrictFPOp()
2322 Node->getOpcode() == ISD::STRICT_FSETCCS) in UnrollStrictFPOp()
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| H A D | LegalizeDAG.cpp | 1069 case ISD::STRICT_FSETCCS: in LegalizeOp()
1077 : Opc == ISD::STRICT_FSETCCS ? 3 in LegalizeOp()
1083 : Opc == ISD::STRICT_FSETCCS ? 1 in LegalizeOp()
4235 case ISD::STRICT_FSETCCS: { in ExpandNode()
4238 Node->getOpcode() == ISD::STRICT_FSETCCS; in ExpandNode()
4239 bool IsSignaling = Node->getOpcode() == ISD::STRICT_FSETCCS; in ExpandNode()
5305 Node->getOpcode() == ISD::STRICT_FSETCCS || in PromoteNode()
5594 case ISD::STRICT_FSETCCS: { in PromoteNode()
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| H A D | SelectionDAGDumper.cpp | 336 case ISD::STRICT_FSETCCS: return "strict_fsetccs"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 1165 case ISD::STRICT_FSETCCS: in SoftenFloatOperand()
1357 Chain, N->getOpcode() == ISD::STRICT_FSETCCS); in SoftenFloatOp_SETCC()
2305 case ISD::STRICT_FSETCCS: in ExpandFloatOperand()
2476 N->getOpcode() == ISD::STRICT_FSETCCS); in ExpandFloatOp_SETCC()
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| H A D | LegalizeVectorTypes.cpp | 3410 case ISD::STRICT_FSETCCS: in SplitVectorOperand()
4416 bool isStrict = Opc == ISD::STRICT_FSETCC || Opc == ISD::STRICT_FSETCCS; in SplitVecOp_VSETCC()
5226 case ISD::STRICT_FSETCCS: in WidenVecRes_StrictFP()
6343 case ISD::STRICT_FSETCCS: in isSETCCOp()
6833 case ISD::STRICT_FSETCCS: Res = WidenVecOp_STRICT_FSETCC(N); break; in WidenVectorOperand()
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| H A D | SelectionDAGISel.cpp | 1327 case ISD::STRICT_FSETCCS: in DoInstructionSelection()
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| H A D | SelectionDAG.cpp | 3817 case ISD::STRICT_FSETCCS: { in computeKnownBits()
5006 case ISD::STRICT_FSETCCS: { in ComputeNumSignBits()
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| H A D | LegalizeIntegerTypes.cpp | 104 case ISD::STRICT_FSETCCS: in PromoteIntegerResult()
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| H A D | DAGCombiner.cpp | 998 N.getOpcode() == ISD::STRICT_FSETCCS)) { in isSetCCEquivalent()
9924 case ISD::STRICT_FSETCCS: { in visitXOR()
9930 N0.getOperand(0), N0Opcode == ISD::STRICT_FSETCCS); in visitXOR()
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| H A D | SelectionDAGBuilder.cpp | 8376 case ISD::STRICT_FSETCCS: { in visitConstrainedFPIntrinsic()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 532 setOperationAction(ISD::STRICT_FSETCCS, MVT::f32, Legal); in PPCTargetLowering()
533 setOperationAction(ISD::STRICT_FSETCCS, MVT::f64, Legal); in PPCTargetLowering()
534 setOperationAction(ISD::STRICT_FSETCCS, MVT::f128, Legal); in PPCTargetLowering()
553 setOperationAction(ISD::STRICT_FSETCCS, MVT::f32, Legal); in PPCTargetLowering()
554 setOperationAction(ISD::STRICT_FSETCCS, MVT::f64, Legal); in PPCTargetLowering()
1316 setOperationAction(ISD::STRICT_FSETCCS, MVT::f128, Custom); in PPCTargetLowering()
3756 Op->getOpcode() == ISD::STRICT_FSETCCS); in LowerSETCC()
12555 case ISD::STRICT_FSETCCS: in LowerOperation()
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| H A D | PPCISelDAGToDAG.cpp | 5473 case ISD::STRICT_FSETCCS: in Select()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 163 setOperationAction(ISD::STRICT_FSETCCS, VT, Custom); in SystemZTargetLowering()
662 setOperationAction(ISD::STRICT_FSETCCS, MVT::v2f64, Custom); in SystemZTargetLowering()
663 setOperationAction(ISD::STRICT_FSETCCS, MVT::v4f32, Custom); in SystemZTargetLowering()
7024 case ISD::STRICT_FSETCCS: in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 459 ISD::STRICT_FSETCC, ISD::STRICT_FSETCCS, ISD::FCANONICALIZE}; in RISCVTargetLowering()
480 ISD::STRICT_FSQRT, ISD::STRICT_FSETCC, ISD::STRICT_FSETCCS, in RISCVTargetLowering()
1127 setOperationAction({ISD::STRICT_FSETCC, ISD::STRICT_FSETCCS, in RISCVTargetLowering()
1535 ISD::STRICT_FSETCC, ISD::STRICT_FSETCCS, ISD::STRICT_FTRUNC, in RISCVTargetLowering()
8202 case ISD::STRICT_FSETCCS: in LowerOperation()
12745 if (Opc == ISD::STRICT_FSETCCS) { in lowerVectorStrictFSetcc()
12751 SDValue Tmp1 = DAG.getNode(ISD::STRICT_FSETCCS, DL, VTList, Chain, Op1, in lowerVectorStrictFSetcc()
12753 SDValue Tmp2 = DAG.getNode(ISD::STRICT_FSETCCS, DL, VTList, Chain, Op2, in lowerVectorStrictFSetcc()
12766 SDValue OEQ = DAG.getNode(ISD::STRICT_FSETCCS, DL, VTList, Chain, Op1, in lowerVectorStrictFSetcc()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 704 def strict_fsetccs : SDNode<"ISD::STRICT_FSETCCS", SDTSetCC, [SDNPHasChain]>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 496 setOperationAction(ISD::STRICT_FSETCCS, VT, Custom); in X86TargetLowering()
714 setOperationAction(ISD::STRICT_FSETCCS, MVT::f16, Promote); in X86TargetLowering()
1187 setOperationAction(ISD::STRICT_FSETCCS, MVT::v2f64, Custom); in X86TargetLowering()
1188 setOperationAction(ISD::STRICT_FSETCCS, MVT::v4f32, Custom); in X86TargetLowering()
1570 setOperationAction(ISD::STRICT_FSETCCS, MVT::v4f64, Custom); in X86TargetLowering()
1571 setOperationAction(ISD::STRICT_FSETCCS, MVT::v8f32, Custom); in X86TargetLowering()
1974 setOperationAction(ISD::STRICT_FSETCCS, MVT::v8f64, Custom); in X86TargetLowering()
1975 setOperationAction(ISD::STRICT_FSETCCS, MVT::v16f32, Custom); in X86TargetLowering()
2280 setOperationAction(ISD::STRICT_FSETCCS, VT, Custom); in X86TargetLowering()
23989 Op.getOpcode() == ISD::STRICT_FSETCCS; in LowerVSETCC()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 199 setOperationAction(ISD::STRICT_FSETCCS, MVT::f32, Legal); in LoongArchTargetLowering()
240 setOperationAction(ISD::STRICT_FSETCCS, MVT::f64, Legal); in LoongArchTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 497 setOperationAction(ISD::STRICT_FSETCCS, MVT::f16, Custom); in AArch64TargetLowering()
498 setOperationAction(ISD::STRICT_FSETCCS, MVT::f32, Custom); in AArch64TargetLowering()
499 setOperationAction(ISD::STRICT_FSETCCS, MVT::f64, Custom); in AArch64TargetLowering()
568 setOperationAction(ISD::STRICT_FSETCCS, MVT::f128, Custom); in AArch64TargetLowering()
2107 setOperationAction(ISD::STRICT_FSETCCS, VT, Expand); in addTypeForNEON()
7235 case ISD::STRICT_FSETCCS: in LowerOperation()
11001 bool IsSignaling = Op.getOpcode() == ISD::STRICT_FSETCCS; in LowerSETCC()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 1452 setOperationAction(ISD::STRICT_FSETCCS, MVT::f16, Custom); in ARMTargetLowering()
1454 setOperationAction(ISD::STRICT_FSETCCS, MVT::f32, Custom); in ARMTargetLowering()
1456 setOperationAction(ISD::STRICT_FSETCCS, MVT::f64, Custom); in ARMTargetLowering()
10578 bool IsSignaling = Op.getOpcode() == ISD::STRICT_FSETCCS; in LowerFSETCC()
10750 case ISD::STRICT_FSETCCS: return LowerFSETCC(Op, DAG); in LowerOperation()
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