Searched refs:STEP_VECTOR (Results 1 – 10 of 10) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 682 STEP_VECTOR, enumerator
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 354 case ISD::STEP_VECTOR: return "step_vector"; in getOperationName()
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| H A D | SelectionDAG.cpp | 2125 ISD::STEP_VECTOR, DL, ResVT, in getStepVector() 3437 case ISD::STEP_VECTOR: { in computeKnownBits() 6340 case ISD::STEP_VECTOR: { in getNode() 6349 case ISD::STEP_VECTOR: in getNode() 6874 case ISD::STEP_VECTOR: in FoldConstantArithmetic() 7100 Ops[0].getOpcode() == ISD::STEP_VECTOR) { in FoldConstantArithmetic() 7420 N2.getOpcode() == ISD::STEP_VECTOR) in canonicalizeCommutativeBinop()
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| H A D | LegalizeVectorTypes.cpp | 1145 case ISD::STEP_VECTOR: in SplitVectorResult() 2065 Lo = DAG.getNode(ISD::STEP_VECTOR, dl, LoVT, Step); in SplitVecRes_STEP_VECTOR() 2075 Hi = DAG.getNode(ISD::STEP_VECTOR, dl, HiVT, Step); in SplitVecRes_STEP_VECTOR() 4688 case ISD::STEP_VECTOR: in WidenVectorResult()
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| H A D | LegalizeVectorOps.cpp | 1685 (!TLI.isOperationLegalOrCustom(ISD::STEP_VECTOR, EVLVecVT) || in ExpandVP_MERGE()
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| H A D | DAGCombiner.cpp | 3155 if (N0.getOpcode() == ISD::STEP_VECTOR && in visitADD() 3156 N1.getOpcode() == ISD::STEP_VECTOR) { in visitADD() 3165 N0.getOperand(1).getOpcode() == ISD::STEP_VECTOR && in visitADD() 3166 N1.getOpcode() == ISD::STEP_VECTOR) { in visitADD() 4366 if (N1.getOpcode() == ISD::STEP_VECTOR && N1.hasOneUse()) { in visitSUB() 4834 if (!UseVP && N0.getOpcode() == ISD::STEP_VECTOR && in visitMUL() 10612 if (N0.getOpcode() == ISD::STEP_VECTOR && in visitSHL()
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| H A D | LegalizeIntegerTypes.cpp | 150 case ISD::STEP_VECTOR: Res = PromoteIntRes_STEP_VECTOR(N); break; in PromoteIntegerResult()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 831 def step_vector : SDNode<"ISD::STEP_VECTOR", SDTypeProfile<1, 1,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1157 ISD::VECREDUCE_ADD, ISD::STEP_VECTOR}); in AArch64TargetLowering() 24261 if (Index.getOpcode() == ISD::STEP_VECTOR) { in findMoreOptimalIndexType() 24267 Index.getOperand(0).getOpcode() == ISD::STEP_VECTOR) { in findMoreOptimalIndexType()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 935 setOperationAction({ISD::STEP_VECTOR, ISD::VECTOR_REVERSE}, VT, Custom); in RISCVTargetLowering() 7806 case ISD::STEP_VECTOR: in LowerOperation()
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