| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 334 SSUBO, enumerator
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| H A D | SelectionDAGNodes.h | 3263 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.h | 101 SADDO, SSUBO, UADDO, USUBO, ADDCARRY, SUBCARRY, enumerator
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| H A D | SystemZISelDAGToDAG.cpp | 1407 case SystemZISD::SSUBO: in tryFoldLoadStoreIntoMemOperand()
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| H A D | SystemZOperators.td | 292 def z_ssubo : SDNode<"SystemZISD::SSUBO", SDT_ZBinaryWithFlags>;
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| H A D | SystemZISelLowering.cpp | 190 setOperationAction(ISD::SSUBO, VT, Custom); in SystemZTargetLowering()
4315 case ISD::SSUBO: in lowerXALUO()
4316 BaseOp = SystemZISD::SSUBO; in lowerXALUO()
6163 case ISD::SSUBO: in LowerOperation()
6399 OPCODE(SSUBO); in getTargetNodeName()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 118 setOperationAction(ISD::SSUBO, VT, Custom); in M68kTargetLowering()
1384 case ISD::SSUBO: in LowerOperation()
1541 case ISD::SSUBO: in isOverflowArithmetic()
1586 case ISD::SSUBO: in lowerOverflowArithmetic()
2466 Cond.getOperand(0).getOpcode() == ISD::SSUBO || in LowerBRCOND()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 345 case ISD::SSUBO: return "ssubo"; in getOperationName()
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| H A D | LegalizeVectorOps.cpp | 443 case ISD::SSUBO: in LegalizeOp()
1033 case ISD::SSUBO: in Expand()
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| H A D | LegalizeIntegerTypes.cpp | 214 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break; in PromoteIntegerResult()
2895 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break; in ExpandIntegerResult()
4481 assert((Node->getOpcode() == ISD::SADDO || Node->getOpcode() == ISD::SSUBO) && in ExpandIntRes_SADDSUBO()
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| H A D | SelectionDAG.cpp | 3889 case ISD::SSUBO: in computeKnownBits()
4712 case ISD::SSUBO: in ComputeNumSignBits()
10176 case ISD::SSUBO: in getNode()
10207 if (Opcode == ISD::USUBO || Opcode == ISD::SSUBO) { in getNode()
12481 Opcode == ISD::USUBO || Opcode == ISD::SSUBO || in UnrollVectorOverflowOp()
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| H A D | LegalizeVectorTypes.cpp | 212 case ISD::SSUBO: in ScalarizeVectorResult()
1311 case ISD::SSUBO: in SplitVectorResult()
4468 case ISD::SSUBO: in WidenVectorResult()
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| H A D | DAGCombiner.cpp | 1849 case ISD::SSUBO: in visit()
3327 return DAG.getNode(ISD::SSUBO, DL, N->getVTList(), in visitADDO()
4205 bool IsSigned = (ISD::SSUBO == N->getOpcode()); in visitSUBO()
4278 TLI.isOperationLegalOrCustom(ISD::SSUBO, N->getValueType(0))) in visitSSUBO_CARRY()
4279 return DAG.getNode(ISD::SSUBO, SDLoc(N), N->getVTList(), N0, N1); in visitSSUBO_CARRY()
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| H A D | LegalizeDAG.cpp | 3974 case ISD::SSUBO: { in ExpandNode()
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| H A D | SelectionDAGBuilder.cpp | 7495 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break; in visitIntrinsicCall()
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| H A D | TargetLowering.cpp | 10357 OverflowOp = ISD::SSUBO; in expandAddSubSat()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 732 setOperationAction({ISD::SADDO, ISD::SSUBO, ISD::UADDO, ISD::USUBO, in initActions()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1571 setOperationAction(ISD::SSUBO, VT, Expand); in HexagonTargetLowering()
1648 ISD::UADDO, ISD::SSUBO, ISD::USUBO, ISD::SMUL_LOHI, ISD::UMUL_LOHI, in HexagonTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 1144 setOperationAction(ISD::SSUBO, MVT::i32, Custom); in ARMTargetLowering()
4957 case ISD::SSUBO: in getARMXALUOOp()
5141 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO || in LowerSELECT()
5723 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO || in LowerBRCOND()
5774 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO || in LowerBR_CC()
10644 case ISD::SSUBO: in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 537 ISD::SREM, ISD::SRL, ISD::SSHLSAT, ISD::SSUBO, in NVPTXTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 701 setOperationAction(ISD::SSUBO, MVT::i32, Custom); in AArch64TargetLowering()
702 setOperationAction(ISD::SSUBO, MVT::i64, Custom); in AArch64TargetLowering()
3994 case ISD::SSUBO: in getAArch64XALUOOp()
6806 case ISD::SSUBO: in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 2435 setOperationAction(ISD::SSUBO, VT, Custom); in X86TargetLowering()
22680 case ISD::SSUBO: in EmitTest()
23973 case ISD::SSUBO: in getX86XALUOOp()
24263 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO || in LowerSELECT()
28189 DAG.getNode(Opcode == ISD::SADDSAT ? ISD::SADDO : ISD::SSUBO, DL, in LowerADDSAT_SUBSAT()
32467 case ISD::SSUBO: in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 291 setOperationAction(ISD::SSUBO, MVT::i32, Custom); in RISCVTargetLowering()
5721 // Custom lower i32 SADDO/SSUBO with RV64LegalI32 so we take advantage of addw. in lowerSADDO_SSUBO()
6273 case ISD::SSUBO: in LowerOperation()
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