| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 347 SSUBO, enumerator
|
| H A D | SelectionDAGNodes.h | 3376 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
|
| H A D | BasicTTIImpl.h | 2531 ISD = ISD::SSUBO; in getTypeBasedIntrinsicInstrCost()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 120 setOperationAction(ISD::SSUBO, VT, Custom); in M68kTargetLowering()
1386 case ISD::SSUBO: in LowerOperation()
1543 case ISD::SSUBO: in isOverflowArithmetic()
1588 case ISD::SSUBO: in lowerOverflowArithmetic()
2467 Cond.getOperand(0).getOpcode() == ISD::SSUBO || in LowerBRCOND()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.h | 101 SADDO, SSUBO, UADDO, USUBO, ADDCARRY, SUBCARRY, enumerator
|
| H A D | SystemZOperators.td | 307 def z_ssubo : SDNode<"SystemZISD::SSUBO", SDT_ZBinaryWithFlags>;
|
| H A D | SystemZISelDAGToDAG.cpp | 1418 case SystemZISD::SSUBO: in tryFoldLoadStoreIntoMemOperand()
|
| H A D | SystemZISelLowering.cpp | 199 setOperationAction(ISD::SSUBO, VT, Custom); in SystemZTargetLowering()
4786 case ISD::SSUBO: in lowerXALUO()
4787 BaseOp = SystemZISD::SSUBO; in lowerXALUO()
7059 case ISD::SSUBO: in LowerOperation()
7402 OPCODE(SSUBO); in getTargetNodeName()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 362 case ISD::SSUBO: return "ssubo"; in getOperationName()
|
| H A D | LegalizeVectorOps.cpp | 457 case ISD::SSUBO: in LegalizeOp()
1164 case ISD::SSUBO: in Expand()
|
| H A D | SelectionDAG.cpp | 4126 case ISD::SSUBO: in computeKnownBits()
4989 case ISD::SSUBO: in ComputeNumSignBits()
5584 case ISD::SSUBO: in canCreateUndefOrPoison()
10722 case ISD::SSUBO: in getNode()
10752 if (Opcode == ISD::USUBO || Opcode == ISD::SSUBO) { in getNode()
13059 Opcode == ISD::USUBO || Opcode == ISD::SSUBO || in UnrollVectorOverflowOp()
|
| H A D | LegalizeIntegerTypes.cpp | 234 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break; in PromoteIntegerResult()
3078 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break; in ExpandIntegerResult()
4705 assert((Node->getOpcode() == ISD::SADDO || Node->getOpcode() == ISD::SSUBO) && in ExpandIntRes_SADDSUBO()
|
| H A D | LegalizeVectorTypes.cpp | 224 case ISD::SSUBO: in ScalarizeVectorResult()
1370 case ISD::SSUBO: in SplitVectorResult()
4837 case ISD::SSUBO: in WidenVectorResult()
|
| H A D | DAGCombiner.cpp | 1907 case ISD::SSUBO: in visit()
3468 return DAG.getNode(ISD::SSUBO, DL, N->getVTList(), in visitADDO()
4535 bool IsSigned = (ISD::SSUBO == N->getOpcode()); in visitSUBO()
4608 TLI.isOperationLegalOrCustom(ISD::SSUBO, N->getValueType(0))) in visitSSUBO_CARRY()
4609 return DAG.getNode(ISD::SSUBO, SDLoc(N), N->getVTList(), N0, N1); in visitSSUBO_CARRY()
|
| H A D | LegalizeDAG.cpp | 4113 case ISD::SSUBO: { in ExpandNode()
|
| H A D | SelectionDAGBuilder.cpp | 7551 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break; in visitIntrinsicCall()
|
| H A D | TargetLowering.cpp | 10849 OverflowOp = ISD::SSUBO; in expandAddSubSat()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 823 setOperationAction({ISD::SADDO, ISD::SSUBO, ISD::UADDO, ISD::USUBO, in initActions()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1639 setOperationAction(ISD::SSUBO, VT, Expand); in HexagonTargetLowering()
1717 ISD::UADDO, ISD::SSUBO, ISD::USUBO, ISD::SMUL_LOHI, ISD::UMUL_LOHI, in HexagonTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 1146 setOperationAction(ISD::SSUBO, MVT::i32, Custom); in ARMTargetLowering()
5021 case ISD::SSUBO: in getARMXALUOOp()
5204 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO || in LowerSELECT()
5803 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO || in LowerBRCOND()
5852 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO || in LowerBR_CC()
10705 case ISD::SSUBO: in LowerOperation()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 648 ISD::SREM, ISD::SRL, ISD::SSHLSAT, ISD::SSUBO, in NVPTXTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 210 setOperationAction(ISD::SSUBO, MVT::i32, Custom); in PPCTargetLowering()
212 setOperationAction(ISD::SSUBO, MVT::i64, Custom); in PPCTargetLowering()
12559 case ISD::SSUBO: in LowerOperation()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 715 setOperationAction(ISD::SSUBO, MVT::i32, Custom); in AArch64TargetLowering()
716 setOperationAction(ISD::SSUBO, MVT::i64, Custom); in AArch64TargetLowering()
4007 case ISD::SSUBO: in getAArch64XALUOOp()
7273 case ISD::SSUBO: in LowerOperation()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 2562 setOperationAction(ISD::SSUBO, VT, Custom); in X86TargetLowering()
23415 case ISD::SSUBO: in EmitTest()
24748 case ISD::SSUBO: in getX86XALUOOp()
25117 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO || in LowerSELECT()
29211 DAG.getNode(Opcode == ISD::SADDSAT ? ISD::SADDO : ISD::SSUBO, DL, in LowerADDSAT_SUBSAT()
33692 case ISD::SSUBO: in LowerOperation()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 12188 case ISD::SSUBO: in isBoolSGPR()
|