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Searched refs:SSE1 (Results 1 – 11 of 11) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86Subtarget.h55 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512 enumerator
193 bool hasSSE1() const { return X86SSELevel >= SSE1; } in hasSSE1()
H A DX86InstrUtils.td567 // SSE1 Instruction Templates:
569 // SSI - SSE1 instructions with XS prefix.
570 // PSI - SSE1 instructions with PS prefix.
571 // PSIi8 - SSE1 instructions with ImmT == Imm8 and PS prefix.
572 // VSSI - SSE1 instructions with XS prefix in AVX form.
573 // VPSI - SSE1 instructions with PS prefix in AVX form, packed single.
H A DX86InstrFPStack.td67 // f32 instructions can use SSE1 and are predicated on FPStackf32 == !SSE1.
H A DX86RegisterInfo.td769 // Ensure that float types are declared first - only float is legal on SSE1.
H A DX86.td69 def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
H A DX86InstrSSE.td224 // SSE1 & 2
719 // This pattern helps select MOVLPS on SSE1 only targets. With SSE2 we'll
781 // This pattern helps select MOVHPS on SSE1 only targets. With SSE2 we'll
2322 /// and later. There are SSE1 v4f32 patterns later.
2844 /// sse_fp_unop_s - SSE1 unops in scalar form
2957 /// sse1_fp_unop_p - SSE1 unops in packed form.
H A DX86InstrCompiler.td573 // SSE1/SSE2.
H A DX86InstrAVX512.td6485 // SSE1. And MOVLPS pattern is even more complex.
/freebsd/contrib/llvm-project/clang/lib/Basic/Targets/
H A DX86.cpp475 .Case("+sse", SSE1) in handleTargetFeatures()
502 if ((FPMath == FP_SSE && SSELevel < SSE1) || in handleTargetFeatures()
503 (FPMath == FP_387 && SSELevel >= SSE1)) { in handleTargetFeatures()
1002 case SSE1: in getTargetDefines()
1022 case SSE1: in getTargetDefines()
1248 .Case("sse", SSELevel >= SSE1) in hasFeature()
H A DX86.h60 SSE1, enumerator
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsX86.td133 // SSE1