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Searched refs:SRegs (Results 1 – 2 of 2) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonFrameLowering.cpp1562 BitVector SRegs(Hexagon::NUM_TARGET_REGS); in assignCalleeSavedSpillSlots() local
1575 SRegs[SR] = true; in assignCalleeSavedSpillSlots()
1578 LLVM_DEBUG(dbgs() << "SRegs.1: "; dump_registers(SRegs, *TRI); in assignCalleeSavedSpillSlots()
1607 SRegs[SR] = false; in assignCalleeSavedSpillSlots()
1611 LLVM_DEBUG(dbgs() << "SRegs.2: "; dump_registers(SRegs, *TRI); in assignCalleeSavedSpillSlots()
1619 for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) { in assignCalleeSavedSpillSlots()
1637 SRegs |= TmpSup; in assignCalleeSavedSpillSlots()
1638 LLVM_DEBUG(dbgs() << "SRegs.4: "; dump_registers(SRegs, *TRI); in assignCalleeSavedSpillSlots()
1643 for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) { in assignCalleeSavedSpillSlots()
1646 if (!SRegs[SR]) in assignCalleeSavedSpillSlots()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp6080 SmallVector<Register, 8> SRegs; in readlaneVGPRToSGPR() local
6086 SRegs.push_back(SGPR); in readlaneVGPRToSGPR()
6093 MIB.addReg(SRegs[i]); in readlaneVGPRToSGPR()