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Searched refs:SReg (Results 1 – 18 of 18) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp100 unsigned getDPRLaneFromSPR(unsigned SReg);
115 unsigned getPrefSPRLane(unsigned SReg);
144 unsigned A15SDOptimizer::getDPRLaneFromSPR(unsigned SReg) { in getDPRLaneFromSPR() argument
145 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, in getDPRLaneFromSPR()
153 unsigned A15SDOptimizer::getPrefSPRLane(unsigned SReg) { in getPrefSPRLane() argument
154 if (!Register::isVirtualRegister(SReg)) in getPrefSPRLane()
155 return getDPRLaneFromSPR(SReg); in getPrefSPRLane()
157 MachineInstr *MI = MRI->getVRegDef(SReg); in getPrefSPRLane()
159 MachineOperand *MO = MI->findRegisterDefOperand(SReg, /*TRI=*/nullptr); in getPrefSPRLane()
165 SReg = MI->getOperand(1).getReg(); in getPrefSPRLane()
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H A DARMBaseInstrInfo.cpp5076 unsigned SReg, unsigned &Lane) { in getCorrespondingDRegAndLane() argument
5077 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass); in getCorrespondingDRegAndLane()
5084 DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass); in getCorrespondingDRegAndLane()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DVirtRegMap.h153 void setIsSplitFromReg(Register virtReg, Register SReg) { in setIsSplitFromReg() argument
154 Virt2SplitMap[virtReg.id()] = SReg; in setIsSplitFromReg()
155 if (hasShape(SReg)) { in setIsSplitFromReg()
156 Virt2ShapeMap[virtReg.id()] = getShape(SReg); in setIsSplitFromReg()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIPreEmitPeephole.cpp128 Register SReg; in optimizeVccBranch() local
130 SReg = Op2.getReg(); in optimizeVccBranch()
135 if (M->definesRegister(SReg, TRI)) in optimizeVccBranch()
137 if (M->modifiesRegister(SReg, TRI)) in optimizeVccBranch()
139 ReadsSreg |= M->readsRegister(SReg, TRI); in optimizeVccBranch()
148 if (A->getOpcode() == And && SReg == CondReg && !ModifiesExec && in optimizeVccBranch()
190 if (SReg == ExecReg) { in optimizeVccBranch()
H A DSIShrinkInstructions.cpp981 Register SReg = Src2->getReg(); in runOnMachineFunction() local
982 if (SReg.isVirtual()) { in runOnMachineFunction()
983 MRI->setRegAllocationHint(SReg, 0, VCCReg); in runOnMachineFunction()
986 if (SReg != VCCReg) in runOnMachineFunction()
H A DSIInstrInfo.cpp1239 Register SReg = MRI.createVirtualRegister(BoolXExecRC); in insertVectorSelect() local
1240 BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg) in insertVectorSelect()
1247 .addReg(SReg); in insertVectorSelect()
1252 Register SReg = MRI.createVirtualRegister(BoolXExecRC); in insertVectorSelect() local
1254 : AMDGPU::S_CSELECT_B64), SReg) in insertVectorSelect()
1262 .addReg(SReg); in insertVectorSelect()
1266 Register SReg = MRI.createVirtualRegister(BoolXExecRC); in insertVectorSelect() local
1268 : AMDGPU::S_CSELECT_B64), SReg) in insertVectorSelect()
1276 .addReg(SReg); in insertVectorSelect()
1282 Register SReg = MRI.createVirtualRegister(BoolXExecRC); in insertVectorSelect() local
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H A DSIInstructions.td1502 // FIXME: Why do only some of these type combinations for SReg and
H A DSIISelLowering.cpp15685 Register SReg = ST.isWave32() in finalizeLowering() local
15689 Info->setSGPRForEXECCopy(SReg); in finalizeLowering()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DRegisterScavenging.cpp382 Register SReg = RS.scavengeRegisterBackwards(RC, DefMI.getIterator(), in spill()
384 MRI.replaceRegWith(VReg, SReg); in spill()
386 return SReg; in spill()
422 Register SReg = scavengeVReg(MRI, RS, Reg, true); in spill()
423 N->addRegisterKilled(SReg, &TRI, false); in spill()
424 RS.setRegUsed(SReg); in spill()
448 Register SReg = scavengeVReg(MRI, RS, Reg, false);
449 I->addRegisterDead(SReg, &TRI, false); in scavengeRegisterBackwards()
537 Register SReg = RS.scavengeRegisterBackwards(RC, DefMI.getIterator(), scavengeVReg() local
577 Register SReg = scavengeVReg(MRI, RS, Reg, true); scavengeFrameVirtualRegsInBlock() local
603 Register SReg = scavengeVReg(MRI, RS, Reg, false); scavengeFrameVirtualRegsInBlock() local
H A DLivePhysRegs.cpp268 if (any_of(TRI.superregs(Reg), [&](MCPhysReg SReg) { in addLiveIns() argument
269 return LiveRegs.contains(SReg) && !MRI.isReserved(SReg); in addLiveIns()
H A DBranchFolding.cpp867 if (any_of(TRI->superregs(Reg), [&](MCPhysReg SReg) { in mergeCommonTails() argument
868 return NewLiveIns.contains(SReg) && !MRI->isReserved(SReg); in mergeCommonTails()
H A DPrologEpilogInserter.cpp1297 for (MCPhysReg SReg : TRI.sub_and_superregs_inclusive(Reg)) in insertZeroCallUsedRegs() local
1298 RegsToZero.reset(SReg); in insertZeroCallUsedRegs()
/freebsd/contrib/llvm-project/clang/include/clang/StaticAnalyzer/Core/PathSensitive/
H A DMemRegion.h1040 ParamVarRegion(const Expr *OE, unsigned Idx, const MemRegion *SReg) in ParamVarRegion() argument
1041 : VarRegion(SReg, ParamVarRegionKind), OriginExpr(OE), Index(Idx) { in ParamVarRegion()
1042 assert(!cast<StackSpaceRegion>(SReg)->getStackFrame()->inTopFrame()); in ParamVarRegion()
1047 unsigned Idx, const MemRegion *SReg);
1317 const SubRegion *SReg) in CXXBaseObjectRegion() argument
1318 : TypedValueRegion(SReg, CXXBaseObjectRegionKind), Data(RD, IsVirtual) { in CXXBaseObjectRegion()
1323 bool IsVirtual, const MemRegion *SReg);
1355 CXXDerivedObjectRegion(const CXXRecordDecl *DerivedD, const SubRegion *SReg) in CXXDerivedObjectRegion() argument
1356 : TypedValueRegion(SReg, CXXDerivedObjectRegionKind), DerivedD(DerivedD) { in CXXDerivedObjectRegion()
1361 assert(SReg->getSymbolicBase() && in CXXDerivedObjectRegion()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.cpp1737 Register SRegHi, SReg, VSReg; in eliminateFrameIndex() local
1744 SRegHi = SReg = is64Bit ? PPC::X4 : PPC::R4; in eliminateFrameIndex()
1745 if (MI.getOperand(0).getReg() == SReg) in eliminateFrameIndex()
1746 SRegHi = SReg = SReg + 1; in eliminateFrameIndex()
1749 .addReg(SReg); in eliminateFrameIndex()
1752 SReg = MF.getRegInfo().createVirtualRegister(RC); in eliminateFrameIndex()
1757 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LI8 : PPC::LI), SReg) in eliminateFrameIndex()
1762 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg) in eliminateFrameIndex()
1767 TII.materializeImmPostRA(MBB, II, dl, SReg, Offset); in eliminateFrameIndex()
1791 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true); in eliminateFrameIndex()
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H A DPPCISelLowering.cpp12367 Register SReg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary() local
12369 BuildMI(BB, dl, TII->get(PPC::AND), SReg) in EmitPartwordAtomicBinary()
12372 unsigned ValueReg = SReg; in EmitPartwordAtomicBinary()
12377 .addReg(SReg) in EmitPartwordAtomicBinary()
/freebsd/contrib/llvm-project/clang/lib/StaticAnalyzer/Core/
H A DMemRegion.cpp320 unsigned Idx, const MemRegion *SReg) { in ProfileRegion() argument
324 ID.AddPointer(SReg); in ProfileRegion()
422 const MemRegion *SReg) { in ProfileRegion() argument
425 ID.AddPointer(SReg); in ProfileRegion()
434 const MemRegion *SReg) { in ProfileRegion() argument
436 ID.AddPointer(SReg); in ProfileRegion()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrInfo.cpp369 Register SReg = in ExpandMOVI() local
371 assert(SReg && "No viable MEGA register available"); in ExpandMOVI()
374 MIB->getOperand(0).setReg(SReg); in ExpandMOVI()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp4931 unsigned SReg = Inst.getOperand(1).getReg(); in expandRotation() local
4939 if (DReg == SReg) { in expandRotation()
4947 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TmpReg, Inst.getLoc(), STI); in expandRotation()
4952 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TReg, Inst.getLoc(), STI); in expandRotation()
4978 TOut.emitRRR(FirstShift, ATReg, SReg, ATReg, Inst.getLoc(), STI); in expandRotation()
4979 TOut.emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), STI); in expandRotation()
4994 unsigned SReg = Inst.getOperand(1).getReg(); in expandRotationImm() local
5006 TOut.emitRRI(Mips::ROTR, DReg, SReg, ShiftValue, Inst.getLoc(), STI); in expandRotationImm()
5011 TOut.emitRRI(Mips::ROTR, DReg, SReg, ImmValue, Inst.getLoc(), STI); in expandRotationImm()
5020 TOut.emitRRI(Mips::SRL, DReg, SReg, 0, Inst.getLoc(), STI); in expandRotationImm()
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