| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | A15SDOptimizer.cpp | 100 unsigned getDPRLaneFromSPR(unsigned SReg);
115 unsigned getPrefSPRLane(unsigned SReg);
144 unsigned A15SDOptimizer::getDPRLaneFromSPR(unsigned SReg) { in getDPRLaneFromSPR() argument
146 TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass); in getDPRLaneFromSPR()
154 unsigned A15SDOptimizer::getPrefSPRLane(unsigned SReg) { in getPrefSPRLane() argument
155 if (!Register::isVirtualRegister(SReg)) in getPrefSPRLane()
156 return getDPRLaneFromSPR(SReg); in getPrefSPRLane()
158 MachineInstr *MI = MRI->getVRegDef(SReg); in getPrefSPRLane()
160 MachineOperand *MO = MI->findRegisterDefOperand(SReg, /*TRI=*/nullptr); in getPrefSPRLane()
166 SReg = MI->getOperand(1).getReg(); in getPrefSPRLane()
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| H A D | ARMBaseInstrInfo.cpp | 4919 unsigned SReg, unsigned &Lane) { in getCorrespondingDRegAndLane() argument
4921 TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass); in getCorrespondingDRegAndLane()
4928 DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass); in getCorrespondingDRegAndLane()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RegisterScavenging.cpp | 381 Register SReg = RS.scavengeRegisterBackwards(RC, DefMI.getIterator(), in scavengeVReg() local
383 MRI.replaceRegWith(VReg, SReg); in scavengeVReg()
385 return SReg; in scavengeVReg()
420 Register SReg = scavengeVReg(MRI, RS, Reg, true); in scavengeFrameVirtualRegsInBlock() local
421 N->addRegisterKilled(SReg, &TRI, false); in scavengeFrameVirtualRegsInBlock()
422 RS.setRegUsed(SReg); in scavengeFrameVirtualRegsInBlock()
445 Register SReg = scavengeVReg(MRI, RS, Reg, false); in scavengeFrameVirtualRegsInBlock() local
446 I->addRegisterDead(SReg, &TRI, false); in scavengeFrameVirtualRegsInBlock()
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| H A D | LivePhysRegs.cpp | 268 if (any_of(TRI.superregs(Reg), [&](MCPhysReg SReg) { in addLiveIns() argument
269 return LiveRegs.contains(SReg) && !MRI.isReserved(SReg); in addLiveIns()
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| H A D | BranchFolding.cpp | 889 if (any_of(TRI->superregs(Reg), [&](MCPhysReg SReg) { in mergeCommonTails() argument
890 return NewLiveIns.contains(SReg) && !MRI->isReserved(SReg); in mergeCommonTails()
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| H A D | PrologEpilogInserter.cpp | 1299 for (MCPhysReg SReg : TRI.sub_and_superregs_inclusive(Reg)) in insertZeroCallUsedRegs() local
1300 RegsToZero.reset(SReg); in insertZeroCallUsedRegs()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIPreEmitPeephole.cpp | 130 Register SReg; in optimizeVccBranch() local
132 SReg = Op2.getReg(); in optimizeVccBranch()
137 if (M->definesRegister(SReg, TRI)) in optimizeVccBranch()
139 if (M->modifiesRegister(SReg, TRI)) in optimizeVccBranch()
141 ReadsSreg |= M->readsRegister(SReg, TRI); in optimizeVccBranch()
150 if (A->getOpcode() == And && SReg == CondReg && !ModifiesExec && in optimizeVccBranch()
192 if (SReg == ExecReg) { in optimizeVccBranch()
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| H A D | SIShrinkInstructions.cpp | 1031 Register SReg = Src2->getReg(); in run() local
1032 if (SReg.isVirtual()) { in run()
1033 MRI->setRegAllocationHint(SReg, 0, VCCReg); in run()
1036 if (SReg != VCCReg) in run()
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| H A D | SIInstrInfo.cpp | 1200 Register SReg = MRI.createVirtualRegister(BoolXExecRC); in insertVectorSelect() local
1201 BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg) in insertVectorSelect()
1208 .addReg(SReg); in insertVectorSelect()
1213 Register SReg = MRI.createVirtualRegister(BoolXExecRC); in insertVectorSelect() local
1215 : AMDGPU::S_CSELECT_B64), SReg) in insertVectorSelect()
1223 .addReg(SReg); in insertVectorSelect()
1227 Register SReg = MRI.createVirtualRegister(BoolXExecRC); in insertVectorSelect() local
1229 : AMDGPU::S_CSELECT_B64), SReg) in insertVectorSelect()
1237 .addReg(SReg); in insertVectorSelect()
1243 Register SReg = MRI.createVirtualRegister(BoolXExecRC); in insertVectorSelect() local
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| H A D | SIInstructions.td | 1681 // FIXME: Why do only some of these type combinations for SReg and
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| H A D | SIISelLowering.cpp | 16758 Register SReg = ST.isWave32() in finalizeLowering() local
16762 Info->setSGPRForEXECCopy(SReg); in finalizeLowering()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | VirtRegMap.h | 139 void setIsSplitFromReg(Register virtReg, Register SReg) { in setIsSplitFromReg() argument
140 Virt2SplitMap[virtReg] = SReg; in setIsSplitFromReg()
141 if (hasShape(SReg)) { in setIsSplitFromReg()
142 Virt2ShapeMap[virtReg] = getShape(SReg); in setIsSplitFromReg()
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| /freebsd/contrib/llvm-project/clang/include/clang/StaticAnalyzer/Core/PathSensitive/ |
| H A D | MemRegion.h | 1068 ParamVarRegion(const Expr *OE, unsigned Idx, const MemRegion *SReg) in ParamVarRegion() argument
1069 : VarRegion(SReg, ParamVarRegionKind), OriginExpr(OE), Index(Idx) { in ParamVarRegion()
1070 assert(!cast<StackSpaceRegion>(SReg)->getStackFrame()->inTopFrame()); in ParamVarRegion()
1075 unsigned Idx, const MemRegion *SReg);
1345 const SubRegion *SReg) in CXXBaseObjectRegion() argument
1346 : TypedValueRegion(SReg, CXXBaseObjectRegionKind), Data(RD, IsVirtual) { in CXXBaseObjectRegion()
1351 bool IsVirtual, const MemRegion *SReg);
1383 CXXDerivedObjectRegion(const CXXRecordDecl *DerivedD, const SubRegion *SReg) in CXXDerivedObjectRegion() argument
1384 : TypedValueRegion(SReg, CXXDerivedObjectRegionKind), DerivedD(DerivedD) { in CXXDerivedObjectRegion()
1389 assert(SReg->getSymbolicBase() && in CXXDerivedObjectRegion()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kInstrInfo.cpp | 366 Register SReg = in ExpandMOVI() local
370 assert(SReg && "No viable MEGA register available"); in ExpandMOVI()
379 MIB->getOperand(0).setReg(SReg); in ExpandMOVI()
392 BuildMI(MBB, MIB.getInstr(), DL, get(M68k::MOVQ), SReg).addImm(~Imm & 0xFF); in ExpandMOVI()
404 BuildMI(MBB, MIB.getInstr(), DL, get(M68k::SUB32ar), SReg) in ExpandMOVI()
405 .addReg(SReg, RegState::Undef) in ExpandMOVI()
406 .addReg(SReg, RegState::Undef); in ExpandMOVI()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCRegisterInfo.cpp | 1848 Register SRegHi, SReg, VSReg; in eliminateFrameIndex() local
1855 SRegHi = SReg = is64Bit ? PPC::X4 : PPC::R4; in eliminateFrameIndex()
1856 if (MI.getOperand(0).getReg() == SReg) in eliminateFrameIndex()
1857 SRegHi = SReg = SReg + 1; in eliminateFrameIndex()
1860 .addReg(SReg); in eliminateFrameIndex()
1863 SReg = MF.getRegInfo().createVirtualRegister(RC); in eliminateFrameIndex()
1868 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LI8 : PPC::LI), SReg) in eliminateFrameIndex()
1873 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg) in eliminateFrameIndex()
1878 TII.materializeImmPostRA(MBB, II, dl, SReg, Offset); in eliminateFrameIndex()
1902 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true); in eliminateFrameIndex()
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| H A D | PPCISelLowering.cpp | 13195 Register SReg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary() local
13197 BuildMI(BB, dl, TII->get(PPC::AND), SReg) in EmitPartwordAtomicBinary()
13200 unsigned ValueReg = SReg; in EmitPartwordAtomicBinary()
13205 .addReg(SReg) in EmitPartwordAtomicBinary()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Frontend/HLSL/ |
| H A D | HLSLRootSignature.h | 31 enum class RegisterType { BReg, TReg, UReg, SReg }; enumerator
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| /freebsd/contrib/llvm-project/clang/lib/StaticAnalyzer/Core/ |
| H A D | MemRegion.cpp | 329 unsigned Idx, const MemRegion *SReg) { in ProfileRegion() argument
333 ID.AddPointer(SReg); in ProfileRegion()
431 const MemRegion *SReg) { in ProfileRegion() argument
434 ID.AddPointer(SReg); in ProfileRegion()
443 const MemRegion *SReg) { in ProfileRegion() argument
445 ID.AddPointer(SReg); in ProfileRegion()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonLoadStoreWidening.cpp | 610 MachineOperand SReg = SecondSt->getOperand(2); in createWideStores() local
611 assert(FReg.isReg() && SReg.isReg() && in createWideStores()
616 MachineInstr *CombI = BuildMI(*MF, DL, CombD, VReg).add(SReg).add(FReg); in createWideStores()
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| /freebsd/contrib/llvm-project/llvm/lib/Frontend/HLSL/ |
| H A D | HLSLRootSignature.cpp | 69 {"s", RegisterType::SReg},
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 4874 MCRegister SReg = Inst.getOperand(1).getReg(); in expandRotation() local
4882 if (DReg == SReg) { in expandRotation()
4890 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TmpReg, Inst.getLoc(), STI); in expandRotation()
4895 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TReg, Inst.getLoc(), STI); in expandRotation()
4921 TOut.emitRRR(FirstShift, ATReg, SReg, ATReg, Inst.getLoc(), STI); in expandRotation()
4922 TOut.emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), STI); in expandRotation()
4937 MCRegister SReg = Inst.getOperand(1).getReg(); in expandRotationImm() local
4949 TOut.emitRRI(Mips::ROTR, DReg, SReg, ShiftValue, Inst.getLoc(), STI); in expandRotationImm()
4954 TOut.emitRRI(Mips::ROTR, DReg, SReg, ImmValue, Inst.getLoc(), STI); in expandRotationImm()
4963 TOut.emitRRI(Mips::SRL, DReg, SReg, 0, Inst.getLoc(), STI); in expandRotationImm()
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| /freebsd/contrib/llvm-project/clang/lib/Parse/ |
| H A D | ParseHLSLRootSignature.cpp | 964 Reg.ViewType = RegisterType::SReg; in parseRegister()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVInstructionSelector.cpp | 1035 for (Register SReg : Srcs) { in selectOpWithSrcs() local
1036 MIB.addUse(SReg); in selectOpWithSrcs()
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