| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVGISel.td | 166 (SRAI (XLenVT (SLLI GPR:$src, 16)), 16)>;
170 (SRAI (XLenVT (SLLI GPR:$src, 48)), 48)>;
172 (SRAI (XLenVT (SLLI GPR:$src, 48)), 48)>;
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| H A D | RISCVISelDAGToDAG.cpp | 1333 SDNode *SRAI = CurDAG->getMachineNode( in Select() local
1334 RISCV::SRAI, DL, VT, SDValue(SLLI, 0), in Select()
1336 ReplaceNode(Node, SRAI); in Select()
1609 SDNode *SRAI = CurDAG->getMachineNode( in Select() local
1610 RISCV::SRAI, DL, VT, X, in Select()
1613 RISCV::SRLI, DL, VT, SDValue(SRAI, 0), in Select()
1627 SDNode *SRAI = CurDAG->getMachineNode( in Select() local
1628 RISCV::SRAI, DL, VT, N0.getOperand(0), in Select()
1631 RISCV::SRLI, DL, VT, SDValue(SRAI, 0), in Select()
3377 RISCV::SRAI, DL, VT, N0.getOperand(0), in selectSHXADDOp()
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| H A D | RISCVOptWInstrs.cpp | 382 case RISCV::SRAI: in isSignExtendingOpW()
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| H A D | RISCVExpandPseudoInsts.cpp | 229 case RISCV::PseudoCCSRAI: NewOpc = RISCV::SRAI; break; in expandCCOp()
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| H A D | RISCVInstrInfo.td | 789 def SRAI : Shift_ri<0b01000, 0b101, "srai">,
1179 (SRAI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt)>;
1449 def : PatGprUimmLog2XLen<sra, SRAI>;
1469 (SRAI (i32 (SLLI $rs, 31)), 31)>, Requires<[IsRV32]>;
1471 (SRAI (i64 (SLLI $rs, 63)), 63)>, Requires<[IsRV64]>;
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| H A D | RISCVRegisterInfo.cpp | 959 case RISCV::SRAI: in getRegAllocationHints()
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| H A D | RISCVInstrInfoC.td | 930 def : CompressPat<(SRAI GPRC:$rs1, GPRC:$rs1, uimmlog2xlennonzero:$imm),
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| H A D | RISCVInstrInfo.cpp | 1660 case RISCV::SRAI: return RISCV::PseudoCCSRAI; break; in getPredicatedOpcode()
4228 case RISCV::SRAI: in simplifyInstruction()
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| /freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/ |
| H A D | RISCVInstructions.h | 144 R_SHAMT_TYPE_INST(SRAI);
278 LWU, LD, SD, SLLI, SRLI, SRAI, ADDIW, SLLIW, SRLIW, SRAIW, ADDW, SUBW, SLLW,
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| H A D | RISCVCInstructions.h | 249 return SRAI{rd, rd, uint8_t(shamt)}; in DecodeC_SRAI()
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| H A D | EmulateInstructionRISCV.cpp | 445 {"SRAI", 0xF800707F, 0x40005013, DecodeRShamtType<SRAI>},
892 bool operator()(SRAI inst) { in operator ()()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsScheduleP5600.td | 437 def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(SRA|SRAI)_[BHWD]$")>;
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| H A D | MipsScheduleGeneric.td | 1558 def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(SRA|SRAI)_[BHWD]$")>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/ |
| H A D | XtensaInstrInfo.td | 151 def SRAI : RRR_Inst<0x00, 0x01, 0x02, (outs AR:$r), (ins AR:$t, uimm5:$sa),
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/ |
| H A D | RISCVAsmParser.cpp | 3594 unsigned SecondOpcode = SignExtend ? RISCV::SRAI : RISCV::SRLI; in emitPseudoExtend()
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