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Searched refs:SPLAT_VECTOR_SPLIT_I64_VL (Results 1 – 4 of 4) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrGISel.td52 // Pseudo equivalent to a RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL. There is no
H A DRISCVISelLowering.h180 SPLAT_VECTOR_SPLIT_I64_VL, enumerator
H A DRISCVISelDAGToDAG.cpp75 case RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL: { in PreprocessISelDAG()
H A DRISCVISelLowering.cpp4287 return DAG.getNode(RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL, DL, VT, Passthru, Lo, in splatPartsI64WithVL()
17255 if (ShAmt.getOpcode() == RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL) { in PerformDAGCombine()
17278 if (ShAmt.getOpcode() == RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL) { in PerformDAGCombine()
20452 NODE_NAME_CASE(SPLAT_VECTOR_SPLIT_I64_VL) in getTargetNodeName()