| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 338 SMULO, enumerator
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| H A D | SelectionDAGNodes.h | 3264 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO));
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 97 for (auto OP : {ISD::SMULO, ISD::UMULO}) { in M68kTargetLowering()
1386 case ISD::SMULO: in LowerOperation()
1543 case ISD::SMULO: in isOverflowArithmetic()
1600 case ISD::SMULO: in lowerOverflowArithmetic()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 347 case ISD::SMULO: return "smulo"; in getOperationName()
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| H A D | LegalizeVectorOps.cpp | 445 case ISD::SMULO: in LegalizeOp()
1037 case ISD::SMULO: in Expand()
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| H A D | LegalizeIntegerTypes.cpp | 217 case ISD::SMULO: in PromoteIntegerResult()
1802 if (N->getOpcode() == ISD::SMULO) { in PromoteIntRes_XMULO()
2899 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break; in ExpandIntegerResult()
4263 unsigned MulOp = Signed ? ISD::SMULO : ISD::UMULO; in ExpandIntRes_MULFIX()
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| H A D | LegalizeVectorTypes.cpp | 214 case ISD::SMULO: in ScalarizeVectorResult()
1313 case ISD::SMULO: in SplitVectorResult()
4470 case ISD::SMULO: in WidenVectorResult()
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| H A D | SelectionDAG.cpp | 3558 case ISD::SMULO: in computeKnownBits()
4716 case ISD::SMULO: in ComputeNumSignBits()
12482 Opcode == ISD::UMULO || Opcode == ISD::SMULO) && in UnrollVectorOverflowOp()
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| H A D | TargetLowering.cpp | 10656 } else if (Signed && isOperationLegalOrCustom(ISD::SMULO, VT)) { in expandFixedPointMul()
10658 DAG.getNode(ISD::SMULO, dl, DAG.getVTList(VT, BoolVT), LHS, RHS); in expandFixedPointMul()
10964 bool isSigned = Node->getOpcode() == ISD::SMULO; in expandMULO()
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| H A D | LegalizeDAG.cpp | 3990 case ISD::SMULO: { in ExpandNode()
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| H A D | SelectionDAGBuilder.cpp | 7497 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break; in visitIntrinsicCall()
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| H A D | DAGCombiner.cpp | 1876 case ISD::SMULO: in visit()
5456 bool IsSigned = (ISD::SMULO == N->getOpcode()); in visitMULO()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1859 setOperationAction(ISD::SMULO, MVT::i64, Custom); in SparcTargetLowering()
3163 assert((opcode == ISD::UMULO || opcode == ISD::SMULO) && "Invalid Opcode."); in LowerUMULO_SMULO()
3165 bool isSigned = (opcode == ISD::SMULO); in LowerUMULO_SMULO()
3291 case ISD::SMULO: return LowerUMULO_SMULO(Op, DAG, *this); in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 733 ISD::SMULO, ISD::UMULO}, in initActions()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 841 setOperationAction({ISD::SMULO, ISD::UMULO}, MVT::i64, Custom); in SITargetLowering()
5865 case ISD::SMULO: in LowerOperation()
6810 bool isSigned = Op.getOpcode() == ISD::SMULO; in lowerXMULO()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 705 setOperationAction(ISD::SMULO, MVT::i32, Custom); in AArch64TargetLowering()
706 setOperationAction(ISD::SMULO, MVT::i64, Custom); in AArch64TargetLowering()
4003 case ISD::SMULO: in getAArch64XALUOOp()
4006 bool IsSigned = Op.getOpcode() == ISD::SMULO; in getAArch64XALUOOp()
6808 case ISD::SMULO: in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 1116 setOperationAction(ISD::SMULO, MVT::v16i8, Custom); in X86TargetLowering()
1362 setOperationAction(ISD::SMULO, MVT::v2i32, Custom); in X86TargetLowering()
1576 setOperationAction(ISD::SMULO, MVT::v32i8, Custom); in X86TargetLowering()
1918 setOperationAction(ISD::SMULO, MVT::v64i8, Custom); in X86TargetLowering()
2437 setOperationAction(ISD::SMULO, VT, Custom); in X86TargetLowering()
23981 case ISD::SMULO: in getX86XALUOOp()
24265 CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) { in LowerSELECT()
28823 bool IsSigned = Op->getOpcode() == ISD::SMULO; in LowerMULO()
32469 case ISD::SMULO: in LowerOperation()
32605 case ISD::SMULO: in ReplaceNodeResults()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 536 ISD::SMIN, ISD::SMULO, ISD::SMUL_LOHI, ISD::SRA, in NVPTXTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 4977 case ISD::SMULO: in getARMXALUOOp()
5720 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) && in LowerBRCOND()
5771 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) && in LowerBR_CC()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 308 setOperationAction(ISD::SMULO, MVT::i32, Custom); in RISCVTargetLowering()
5742 // Custom lower i32 SMULO with RV64LegalI32 so we take advantage of mulw. in lowerSMULO()
6275 case ISD::SMULO: in LowerOperation()
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