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Searched refs:SMULO (Results 1 – 20 of 20) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp3753 { ISD::SMULO, MVT::v32i16, { 3, 6, 4, 4 } }, in getIntrinsicInstrCost()
3754 { ISD::SMULO, MVT::v64i8, { 8, 21, 17, 18 } }, in getIntrinsicInstrCost()
3835 { ISD::SMULO, MVT::v8i64, { 44, 44, 81, 93 } }, in getIntrinsicInstrCost()
3836 { ISD::SMULO, MVT::v16i32, { 5, 12, 9, 11 } }, in getIntrinsicInstrCost()
3837 { ISD::SMULO, MVT::v32i16, { 6, 12, 17, 17 } }, in getIntrinsicInstrCost()
3838 { ISD::SMULO, MVT::v64i8, { 22, 28, 42, 42 } }, in getIntrinsicInstrCost()
3997 { ISD::SMULO, MVT::v4i64, { 20, 20, 33, 37 } }, in getIntrinsicInstrCost()
3998 { ISD::SMULO, MVT::v2i64, { 8, 8, 13, 15 } }, in getIntrinsicInstrCost()
3999 { ISD::SMULO, MVT::v8i32, { 8, 20, 13, 24 } }, in getIntrinsicInstrCost()
4000 { ISD::SMULO, MVT::v4i32, { 5, 15, 11, 12 } }, in getIntrinsicInstrCost()
[all …]
H A DX86ISelLowering.cpp1135 setOperationAction(ISD::SMULO, MVT::v16i8, Custom); in X86TargetLowering()
1383 setOperationAction(ISD::SMULO, MVT::v2i32, Custom); in X86TargetLowering()
1600 setOperationAction(ISD::SMULO, MVT::v32i8, Custom); in X86TargetLowering()
1950 setOperationAction(ISD::SMULO, MVT::v64i8, Custom); in X86TargetLowering()
2564 setOperationAction(ISD::SMULO, VT, Custom); in X86TargetLowering()
24756 case ISD::SMULO: in getX86XALUOOp()
25119 CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) { in LowerSELECT()
29887 bool IsSigned = Op->getOpcode() == ISD::SMULO; in LowerMULO()
33694 case ISD::SMULO: in LowerOperation()
33833 case ISD::SMULO: in ReplaceNodeResults()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h351 SMULO, enumerator
H A DSelectionDAGNodes.h3377 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO));
H A DBasicTTIImpl.h2540 ISD = ISD::SMULO; in getTypeBasedIntrinsicInstrCost()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp99 for (auto OP : {ISD::SMULO, ISD::UMULO}) { in M68kTargetLowering()
1388 case ISD::SMULO: in LowerOperation()
1545 case ISD::SMULO: in isOverflowArithmetic()
1602 case ISD::SMULO: in lowerOverflowArithmetic()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp364 case ISD::SMULO: return "smulo"; in getOperationName()
H A DLegalizeVectorOps.cpp459 case ISD::SMULO: in LegalizeOp()
1168 case ISD::SMULO: in Expand()
H A DLegalizeIntegerTypes.cpp237 case ISD::SMULO: in PromoteIntegerResult()
1847 if (N->getOpcode() == ISD::SMULO) { in PromoteIntRes_XMULO()
3082 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break; in ExpandIntegerResult()
4487 unsigned MulOp = Signed ? ISD::SMULO : ISD::UMULO; in ExpandIntRes_MULFIX()
H A DLegalizeVectorTypes.cpp226 case ISD::SMULO: in ScalarizeVectorResult()
1372 case ISD::SMULO: in SplitVectorResult()
4839 case ISD::SMULO: in WidenVectorResult()
H A DSelectionDAG.cpp3801 case ISD::SMULO: in computeKnownBits()
4991 case ISD::SMULO: in ComputeNumSignBits()
5585 case ISD::SMULO: in canCreateUndefOrPoison()
13060 Opcode == ISD::UMULO || Opcode == ISD::SMULO) && in UnrollVectorOverflowOp()
H A DTargetLowering.cpp11155 } else if (Signed && isOperationLegalOrCustom(ISD::SMULO, VT)) { in expandFixedPointMul()
11157 DAG.getNode(ISD::SMULO, dl, DAG.getVTList(VT, BoolVT), LHS, RHS); in expandFixedPointMul()
11466 bool isSigned = Node->getOpcode() == ISD::SMULO; in expandMULO()
H A DLegalizeDAG.cpp4129 case ISD::SMULO: { in ExpandNode()
H A DSelectionDAGBuilder.cpp7553 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break; in visitIntrinsicCall()
H A DDAGCombiner.cpp1934 case ISD::SMULO: in visit()
5831 bool IsSigned = (ISD::SMULO == N->getOpcode()); in visitMULO()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp824 ISD::SMULO, ISD::UMULO}, in initActions()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp869 setOperationAction({ISD::SMULO, ISD::UMULO}, MVT::i64, Custom); in SITargetLowering()
6212 case ISD::SMULO: in LowerOperation()
7366 bool isSigned = Op.getOpcode() == ISD::SMULO; in lowerXMULO()
12190 case ISD::SMULO: in isBoolSGPR()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp647 ISD::SMIN, ISD::SMULO, ISD::SMUL_LOHI, ISD::SRA, in NVPTXTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp719 setOperationAction(ISD::SMULO, MVT::i32, Custom); in AArch64TargetLowering()
720 setOperationAction(ISD::SMULO, MVT::i64, Custom); in AArch64TargetLowering()
4016 case ISD::SMULO: in getAArch64XALUOOp()
4019 bool IsSigned = Op.getOpcode() == ISD::SMULO; in getAArch64XALUOOp()
7275 case ISD::SMULO: in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp5041 case ISD::SMULO: in getARMXALUOOp()
5800 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) && in LowerBRCOND()
5849 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) && in LowerBR_CC()