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Searched refs:SLT (Results 1 – 15 of 15) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUTargetTransformInfo.cpp541 MVT::SimpleValueType SLT = LT.second.getScalarType().SimpleTy; in getArithmeticInstrCost() local
547 if (SLT == MVT::i64) in getArithmeticInstrCost()
550 if (ST->has16BitInsts() && SLT == MVT::i16) in getArithmeticInstrCost()
560 if (SLT == MVT::i64) { in getArithmeticInstrCost()
565 if (ST->has16BitInsts() && SLT == MVT::i16) in getArithmeticInstrCost()
571 if (SLT == MVT::i64) { in getArithmeticInstrCost()
576 if (ST->has16BitInsts() && SLT == MVT::i16) in getArithmeticInstrCost()
590 if (ST->hasMadMacF32Insts() && SLT == MVT::f32 && !HasFP32Denormals) in getArithmeticInstrCost()
592 if (ST->has16BitInsts() && SLT == MVT::f16 && !HasFP64FP16Denormals) in getArithmeticInstrCost()
606 if (ST->hasPackedFP32Ops() && SLT == MVT::f32) in getArithmeticInstrCost()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsExpandPseudo.cpp311 unsigned LL, SC, SLT, SLTu, OR, MOVN, MOVZ, SELNEZ, SELEQZ; in expandAtomicBinOpSubword() local
319 SLT = Mips::SLT_MM; in expandAtomicBinOpSubword()
331 SLT = Mips::SLT; in expandAtomicBinOpSubword()
474 unsigned SLTScratch4 = IsUnsigned ? SLTu : SLT; in expandAtomicBinOpSubword()
622 unsigned LL, SC, ZERO, BEQ, SLT, SLTu, OR, MOVN, MOVZ, SELNEZ, SELEQZ; in expandAtomicBinOp() local
629 SLT = Mips::SLT_MM; in expandAtomicBinOp()
644 SLT = Mips::SLT; in expandAtomicBinOp()
659 SLT = Mips::SLT64; in expandAtomicBinOp()
779 unsigned SLTScratch2 = IsUnsigned ? SLTu : SLT; in expandAtomicBinOp()
H A DMipsCondMov.td199 defm : MovzPats0<GPR32, GPR32, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>,
204 defm : MovzPats0<GPR32, GPR64, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>,
232 defm : MovzPats0<GPR32, FGR32, MOVZ_I_S, SLT, SLTu, SLTi, SLTiu>,
244 defm : MovzPats0<GPR32, AFGR64, MOVZ_I_D32, SLT, SLTu, SLTi, SLTiu>,
251 defm : MovzPats0<GPR32, FGR64, MOVZ_I_D64, SLT, SLTu, SLTi, SLTiu>,
H A DMipsInstructionSelector.cpp782 Instructions.emplace_back(Mips::SLT, ICMPReg, RHS, LHS); in select()
785 Instructions.emplace_back(Mips::SLT, Temp, LHS, RHS); in select()
789 Instructions.emplace_back(Mips::SLT, ICMPReg, LHS, RHS); in select()
792 Instructions.emplace_back(Mips::SLT, Temp, RHS, LHS); in select()
H A DMipsFastISel.cpp678 emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
681 emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
685 emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
691 emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
H A DMipsInstrInfo.td2067 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>,
2733 (SLT GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>, ISA_MIPS1;
2736 (SLT GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>, ISA_MIPS1;
3285 defm : BrcondPats<GPR32, BEQ, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>,
3339 defm : SetlePats<GPR32, XORi, SLT, SLTu>, ISA_MIPS1;
3340 defm : SetgtPats<GPR32, SLT, SLTu>, ISA_MIPS1;
3341 defm : SetgePats<GPR32, XORi, SLT, SLTu>, ISA_MIPS1;
H A DMipsScheduleP5600.td225 SEB, SEH, SLT, SLTu, SLL, SRA, SRL, XORi,
H A DMips16InstrInfo.td1215 // Format: SLT rx, ry MIPS16e
1829 // x >= k to x > (k - 1) and then use SLT
H A DMipsScheduleGeneric.td50 SLLV, SLT, SLTi, SLTiu, SLTu, SRA, SRAV, SRL,
/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/
H A DRISCVInstructions.h130 R_TYPE_INST(SLT);
277 SLTIU, XORI, ORI, ANDI, ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND,
H A DEmulateInstructionRISCV.cpp449 {"SLT", 0xFE00707F, 0x2033, DecodeRType<SLT>},
811 bool operator()(SLT inst) { in operator ()()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchOptWInstrs.cpp332 case LoongArch::SLT: in isSignExtendingOpW()
H A DLoongArchInstrInfo.td757 def SLT : ALU_3R<0x00120000>;
1393 def : PatGprGpr<setlt, SLT>;
1423 def : Pat<(setgt GPR:$rj, GPR:$rk), (SLT GPR:$rk, GPR:$rj)>;
1424 def : Pat<(setge GPR:$rj, GPR:$rk), (XORI (SLT GPR:$rj, GPR:$rk), 1)>;
1425 def : Pat<(setle GPR:$rj, GPR:$rk), (XORI (SLT GPR:$rk, GPR:$rj), 1)>;
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.td675 def SLT : ALU_rr<0b0000000, 0b010, "slt">,
898 def : InstAlias<"sltz $rd, $rs", (SLT GPR:$rd, GPR:$rs, X0)>;
899 def : InstAlias<"sgtz $rd, $rs", (SLT GPR:$rd, X0, GPR:$rs)>;
903 def : InstAlias<"sgt $rd, $rs, $rt", (SLT GPR:$rd, GPR:$rt, GPR:$rs), 0>;
1375 def : PatGprGpr<setlt, SLT>;
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp4213 TOut.emitRRR(IsUnsigned ? Mips::SLTu : Mips::SLT, ATRegNum, in expandCondBranches()
4618 OpCode = Mips::SLT; in expandSge()
4653 OpRegCode = Mips::SLT; in expandSgeImm()
4710 OpCode = Mips::SLT; in expandSgtImm()
4755 OpCode = Mips::SLT; in expandSle()
4790 OpRegCode = Mips::SLT; in expandSleImm()
4868 FinalOpcode = Mips::SLT; in expandAliasImmediate()