Home
last modified time | relevance | path

Searched refs:SLT (Results 1 – 17 of 17) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUTargetTransformInfo.cpp543 MVT::SimpleValueType SLT = LT.second.getScalarType().SimpleTy; in getArithmeticInstrCost() local
549 if (SLT == MVT::i64) in getArithmeticInstrCost()
552 if (ST->has16BitInsts() && SLT == MVT::i16) in getArithmeticInstrCost()
562 if (SLT == MVT::i64) { in getArithmeticInstrCost()
567 if (ST->has16BitInsts() && SLT == MVT::i16) in getArithmeticInstrCost()
573 if (SLT == MVT::i64) { in getArithmeticInstrCost()
578 if (ST->has16BitInsts() && SLT == MVT::i16) in getArithmeticInstrCost()
592 if (ST->hasMadMacF32Insts() && SLT == MVT::f32 && !HasFP32Denormals) in getArithmeticInstrCost()
594 if (ST->has16BitInsts() && SLT == MVT::f16 && !HasFP64FP16Denormals) in getArithmeticInstrCost()
608 if (ST->hasPackedFP32Ops() && SLT == MVT::f32) in getArithmeticInstrCost()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsExpandPseudo.cpp310 unsigned LL, SC, SLT, SLTu, OR, MOVN, MOVZ, SELNEZ, SELEQZ; in expandAtomicBinOpSubword() local
318 SLT = Mips::SLT_MM; in expandAtomicBinOpSubword()
330 SLT = Mips::SLT; in expandAtomicBinOpSubword()
494 unsigned SLTScratch4 = IsUnsigned ? SLTu : SLT; in expandAtomicBinOpSubword()
717 unsigned LL, SC, ZERO, BEQ, SLT, SLTu, OR, MOVN, MOVZ, SELNEZ, SELEQZ; in expandAtomicBinOp() local
724 SLT = Mips::SLT_MM; in expandAtomicBinOp()
739 SLT = Mips::SLT; in expandAtomicBinOp()
754 SLT = Mips::SLT64; in expandAtomicBinOp()
895 unsigned SLTScratch2 = IsUnsigned ? SLTu : SLT; in expandAtomicBinOp()
H A DMipsCondMov.td199 defm : MovzPats0<GPR32, GPR32, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>,
204 defm : MovzPats0<GPR32, GPR64, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>,
232 defm : MovzPats0<GPR32, FGR32, MOVZ_I_S, SLT, SLTu, SLTi, SLTiu>,
244 defm : MovzPats0<GPR32, AFGR64, MOVZ_I_D32, SLT, SLTu, SLTi, SLTiu>,
251 defm : MovzPats0<GPR32, FGR64, MOVZ_I_D64, SLT, SLTu, SLTi, SLTiu>,
H A DMipsInstructionSelector.cpp782 Instructions.emplace_back(Mips::SLT, ICMPReg, RHS, LHS); in select()
785 Instructions.emplace_back(Mips::SLT, Temp, LHS, RHS); in select()
789 Instructions.emplace_back(Mips::SLT, ICMPReg, LHS, RHS); in select()
792 Instructions.emplace_back(Mips::SLT, Temp, RHS, LHS); in select()
H A DMipsFastISel.cpp676 emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
679 emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
683 emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
689 emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
H A DMipsInstrInfo.td2079 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>,
2745 (SLT GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>, ISA_MIPS1;
2748 (SLT GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>, ISA_MIPS1;
3297 defm : BrcondPats<GPR32, BEQ, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>,
3351 defm : SetlePats<GPR32, XORi, SLT, SLTu>, ISA_MIPS1;
3352 defm : SetgtPats<GPR32, SLT, SLTu>, ISA_MIPS1;
3353 defm : SetgePats<GPR32, XORi, SLT, SLTu>, ISA_MIPS1;
H A DMipsScheduleI6400.td120 SELEQZ, SELEQZ64, SELNEZ, SELNEZ64, SLL, SLLV, SLT, SLTi, SLTiu, SLTu, SRA, SRAV,
H A DMipsScheduleP5600.td225 SEB, SEH, SLT, SLTu, SLL, SRA, SRL, XORi,
H A DMips16InstrInfo.td1215 // Format: SLT rx, ry MIPS16e
1829 // x >= k to x > (k - 1) and then use SLT
H A DMipsScheduleGeneric.td50 SLLV, SLT, SLTi, SLTiu, SLTu, SRA, SRAV, SRL,
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVGISel.td51 (SLT GPR:$rs1, GPR:$rs2)>;
74 (SLT GPR:$rs2, GPR:$rs1)>;
82 (XORI (SLT GPR:$rs1, GPR:$rs2), 1)>;
90 (XORI (SLT GPR:$rs2, GPR:$rs1), 1)>;
H A DRISCVInstrInfo.td799 def SLT : ALU_rr<0b0000000, 0b010, "slt">,
1043 def : InstAlias<"sltz $rd, $rs", (SLT GPR:$rd, GPR:$rs, X0)>;
1044 def : InstAlias<"sgtz $rd, $rs", (SLT GPR:$rd, X0, GPR:$rs)>;
1048 def : InstAlias<"sgt $rd, $rs, $rt", (SLT GPR:$rd, GPR:$rt, GPR:$rs), 0>;
1605 def : PatGprGpr<setlt, SLT>;
/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/
H A DRISCVInstructions.h130 R_TYPE_INST(SLT);
277 SLTIU, XORI, ORI, ANDI, ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND,
H A DEmulateInstructionRISCV.cpp449 {"SLT", 0xFE00707F, 0x2033, DecodeRType<SLT>},
812 bool operator()(SLT inst) { in operator ()()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchOptWInstrs.cpp362 case LoongArch::SLT: in isSignExtendingOpW()
H A DLoongArchInstrInfo.td807 def SLT : ALU_3R<0x00120000>;
1464 def : PatGprGpr<setlt, SLT>;
1494 def : Pat<(setgt GPR:$rj, GPR:$rk), (SLT GPR:$rk, GPR:$rj)>;
1495 def : Pat<(setge GPR:$rj, GPR:$rk), (XORI (SLT GPR:$rj, GPR:$rk), 1)>;
1496 def : Pat<(setle GPR:$rj, GPR:$rk), (XORI (SLT GPR:$rk, GPR:$rj), 1)>;
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp4156 TOut.emitRRR(IsUnsigned ? Mips::SLTu : Mips::SLT, ATRegNum, in expandCondBranches()
4561 OpCode = Mips::SLT; in expandSge()
4596 OpRegCode = Mips::SLT; in expandSgeImm()
4653 OpCode = Mips::SLT; in expandSgtImm()
4698 OpCode = Mips::SLT; in expandSle()
4733 OpRegCode = Mips::SLT; in expandSleImm()
4811 FinalOpcode = Mips::SLT; in expandAliasImmediate()