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Searched refs:SINT_TO_FP (Results 1 – 25 of 41) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp705 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, in getCastInstrCost()
708 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, in getCastInstrCost()
710 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 }, in getCastInstrCost()
712 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, in getCastInstrCost()
714 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, in getCastInstrCost()
716 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, in getCastInstrCost()
718 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, in getCastInstrCost()
720 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, in getCastInstrCost()
722 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, in getCastInstrCost()
724 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 }, in getCastInstrCost()
[all …]
H A DARMISelLowering.cpp190 setOperationAction(ISD::SINT_TO_FP, VT, Custom); in addTypeForNEON()
195 setOperationAction(ISD::SINT_TO_FP, VT, Expand); in addTypeForNEON()
321 setOperationAction(ISD::SINT_TO_FP, VT, Expand); in addMVEVectorTypes()
480 setOperationAction(ISD::SINT_TO_FP, VT, Expand); in addMVEVectorTypes()
491 setOperationAction(ISD::SINT_TO_FP, MVT::v2i1, Expand); in addMVEVectorTypes()
950 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom); in ARMTargetLowering()
951 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Custom); in ARMTargetLowering()
1077 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in ARMTargetLowering()
6076 case ISD::SINT_TO_FP: in LowerVectorINT_TO_FP()
6078 Opc = ISD::SINT_TO_FP; in LowerVectorINT_TO_FP()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp2397 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, { 1, 1, 1, 1 } }, in getCastInstrCost()
2398 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, { 1, 1, 1, 1 } }, in getCastInstrCost()
2513 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, { 4, 1, 1, 1 } }, in getCastInstrCost()
2514 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, { 3, 1, 1, 1 } }, in getCastInstrCost()
2515 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v16i8, { 2, 1, 1, 1 } }, in getCastInstrCost()
2516 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, { 1, 1, 1, 1 } }, in getCastInstrCost()
2517 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, { 2, 1, 1, 1 } }, in getCastInstrCost()
2518 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, { 1, 1, 1, 1 } }, in getCastInstrCost()
2519 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, { 1, 1, 1, 1 } }, in getCastInstrCost()
2520 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, { 1, 1, 1, 1 } }, in getCastInstrCost()
[all …]
H A DX86ISelLowering.cpp260 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote); in X86TargetLowering()
264 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Custom); in X86TargetLowering()
267 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in X86TargetLowering()
271 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in X86TargetLowering()
1021 setOperationAction(ISD::SINT_TO_FP, VT, Expand); in X86TargetLowering()
1241 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Custom); in X86TargetLowering()
1243 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom); in X86TargetLowering()
1253 setOperationAction(ISD::SINT_TO_FP, MVT::v2f32, Custom); in X86TargetLowering()
1413 setOperationAction(ISD::SINT_TO_FP, MVT::v4i64, Custom); in X86TargetLowering()
1492 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Custom); in X86TargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp3232 {ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1}, in getCastInstrCost()
3233 {ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1}, in getCastInstrCost()
3234 {ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1}, in getCastInstrCost()
3240 {ISD::SINT_TO_FP, MVT::nxv2f16, MVT::nxv2i8, in getCastInstrCost()
3242 {ISD::SINT_TO_FP, MVT::nxv2f16, MVT::nxv2i16, SVE_FCVT_COST}, in getCastInstrCost()
3243 {ISD::SINT_TO_FP, MVT::nxv2f16, MVT::nxv2i32, SVE_FCVT_COST}, in getCastInstrCost()
3244 {ISD::SINT_TO_FP, MVT::nxv2f16, MVT::nxv2i64, SVE_FCVT_COST}, in getCastInstrCost()
3252 {ISD::SINT_TO_FP, MVT::nxv4f16, MVT::nxv4i8, in getCastInstrCost()
3254 {ISD::SINT_TO_FP, MVT::nxv4f16, MVT::nxv4i16, SVE_FCVT_COST}, in getCastInstrCost()
3255 {ISD::SINT_TO_FP, MVT::nxv4f16, MVT::nxv4i32, SVE_FCVT_COST}, in getCastInstrCost()
[all …]
H A DAArch64ISelLowering.cpp590 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in AArch64TargetLowering()
591 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in AArch64TargetLowering()
592 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom); in AArch64TargetLowering()
1131 setTargetDAGCombine({ISD::ADD, ISD::ABS, ISD::SUB, ISD::XOR, ISD::SINT_TO_FP, in AArch64TargetLowering()
1257 {ISD::FP_TO_SINT, ISD::FP_TO_UINT, ISD::SINT_TO_FP, ISD::UINT_TO_FP, in AArch64TargetLowering()
1266 setOperationPromotedToType(ISD::SINT_TO_FP, MVT::v4i8, MVT::v4i32); in AArch64TargetLowering()
1271 for (auto Op : {ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::STRICT_SINT_TO_FP, in AArch64TargetLowering()
1280 setOperationAction(ISD::SINT_TO_FP, MVT::v8i8, Custom); in AArch64TargetLowering()
1282 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Custom); in AArch64TargetLowering()
1284 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom); in AArch64TargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DConstrainedOps.def58 DAG_INSTRUCTION(SIToFP, 1, 1, experimental_constrained_sitofp, SINT_TO_FP)
H A DVPIntrinsics.def484 HELPER_REGISTER_FP_CAST_VP(sitofp, VP_SINT_TO_FP, SIToFP, SINT_TO_FP)
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h862 SINT_TO_FP, enumerator
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp258 setOperationAction(ISD::SINT_TO_FP, T, Custom); in initializeHVXLowering()
333 setOperationAction(ISD::SINT_TO_FP, T, Custom); in initializeHVXLowering()
438 setOperationAction(ISD::SINT_TO_FP, VecTy, Custom); in initializeHVXLowering()
2339 assert(Op.getOpcode() == ISD::SINT_TO_FP || in LowerHvxIntToFp()
2714 Opc == ISD::SINT_TO_FP || Opc == ISD::UINT_TO_FP); in EqualizeFpIntConversion()
2724 bool Signed = Opc == ISD::FP_TO_SINT || Opc == ISD::SINT_TO_FP; in EqualizeFpIntConversion()
2865 assert(Opc == ISD::SINT_TO_FP || Opc == ISD::UINT_TO_FP); in ExpandHvxIntToFp()
2899 bool Signed = Opc == ISD::SINT_TO_FP; in ExpandHvxIntToFp()
3191 case ISD::SINT_TO_FP: in LowerHvxOperation()
3273 case ISD::SINT_TO_FP: in LowerHvxOperation()
[all …]
H A DHexagonISelLowering.cpp1876 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote); in HexagonTargetLowering()
1877 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote); in HexagonTargetLowering()
1878 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote); in HexagonTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp497 case ISD::SINT_TO_FP: in LegalizeOp()
713 case ISD::SINT_TO_FP: in Promote()
1839 if (((!IsStrict && TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == in ExpandUINT_TO_FLOAT()
1923 SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, DstVT, HI); in ExpandUINT_TO_FLOAT()
1925 SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, DstVT, LO); in ExpandUINT_TO_FLOAT()
H A DLegalizeDAG.cpp1034 case ISD::SINT_TO_FP: in LegalizeOp()
2673 Node->getOpcode() == ISD::SINT_TO_FP); in ExpandLegalINT_TO_FP()
2802 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Or); in ExpandLegalINT_TO_FP()
2804 Fast = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); in ExpandLegalINT_TO_FP()
2827 Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); in ExpandLegalINT_TO_FP()
2892 bool IsSigned = N->getOpcode() == ISD::SINT_TO_FP || in PromoteLegalINT_TO_FP()
2897 unsigned SIntOp = IsStrict ? ISD::STRICT_SINT_TO_FP : ISD::SINT_TO_FP; in PromoteLegalINT_TO_FP()
3463 case ISD::SINT_TO_FP: in ExpandNode()
4879 DAG.getNode(ISD::SINT_TO_FP, SDLoc(Node), Node->getValueType(0), in ConvertNodeToLibcall()
5016 case ISD::SINT_TO_FP: in ConvertNodeToLibcall()
[all …]
H A DLegalizeFloatTypes.cpp166 case ISD::SINT_TO_FP: in SoftenFloatResult()
1077 bool Signed = N->getOpcode() == ISD::SINT_TO_FP || in SoftenFloatRes_XINT_TO_FP()
1634 case ISD::SINT_TO_FP: in ExpandFloatResult()
2170 bool isSigned = N->getOpcode() == ISD::SINT_TO_FP || in ExpandFloatRes_XINT_TO_FP()
2902 case ISD::SINT_TO_FP: in PromoteFloatResult()
3385 case ISD::SINT_TO_FP: in SoftPromoteHalfResult()
H A DSelectionDAGDumper.cpp408 case ISD::SINT_TO_FP: return "sint_to_fp"; in getOperationName()
H A DFastISel.cpp311 Reg = fastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, in materializeConstant()
1848 return selectCast(I, ISD::SINT_TO_FP); in selectOperator()
H A DLegalizeVectorTypes.cpp128 case ISD::SINT_TO_FP: in ScalarizeVectorResult()
759 case ISD::SINT_TO_FP: in ScalarizeVectorOperand()
1261 case ISD::SINT_TO_FP: in SplitVectorResult()
3453 case ISD::SINT_TO_FP: in SplitVectorOperand()
4875 case ISD::SINT_TO_FP: in WidenVectorResult()
6864 case ISD::SINT_TO_FP: in WidenVectorOperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaISelLowering.cpp90 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); in XtensaTargetLowering()
232 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal); in XtensaTargetLowering()
239 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); in XtensaTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp284 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote); in PPCTargetLowering()
285 AddPromotedToType(ISD::SINT_TO_FP, MVT::i1, RegVT); in PPCTargetLowering()
301 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom); in PPCTargetLowering()
549 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal); in PPCTargetLowering()
563 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); in PPCTargetLowering()
705 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in PPCTargetLowering()
713 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in PPCTargetLowering()
736 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in PPCTargetLowering()
746 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in PPCTargetLowering()
935 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); in PPCTargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp205 setTargetDAGCombine({ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_EXTEND, in WebAssemblyTargetLowering()
297 {ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT}) in WebAssemblyTargetLowering()
2384 case ISD::SINT_TO_FP: in LowerConvertLow()
2919 N->getOpcode() == ISD::SINT_TO_FP); in performVectorExtendToFPCombine()
3518 case ISD::SINT_TO_FP: in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1679 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in SparcTargetLowering()
1681 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in SparcTargetLowering()
3115 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG, *this, in LowerOperation()
3483 case ISD::SINT_TO_FP: in ReplaceNodeResults()
3490 libCall = ((N->getOpcode() == ISD::SINT_TO_FP) in ReplaceNodeResults()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp502 {ISD::UINT_TO_FP, ISD::SINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT}, in AMDGPUTargetLowering()
526 ISD::ROTR, ISD::SUB, ISD::SINT_TO_FP, in AMDGPUTargetLowering()
1457 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); in LowerOperation()
1985 ISD::NodeType ToFp = Sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP; in LowerDIVREM24()
3361 (Signed && Subtarget->isGCN()) ? ISD::SINT_TO_FP : ISD::UINT_TO_FP; in LowerINT_TO_FP32()
3398 SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, in LowerINT_TO_FP64()
3469 return DAG.getNode(ISD::SINT_TO_FP, DL, DestVT, Ext); in LowerSINT_TO_FP()
3474 SDValue ToF32 = DAG.getNode(ISD::SINT_TO_FP, SL, MVT::f32, Src); in LowerSINT_TO_FP()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp233 ISD::SINT_TO_FP, ISD::STRICT_SINT_TO_FP}) in SystemZTargetLowering()
297 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom); in SystemZTargetLowering()
505 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal); in SystemZTargetLowering()
506 setOperationAction(ISD::SINT_TO_FP, MVT::v2f64, Legal); in SystemZTargetLowering()
525 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); in SystemZTargetLowering()
526 setOperationAction(ISD::SINT_TO_FP, MVT::v4f32, Legal); in SystemZTargetLowering()
792 ISD::SINT_TO_FP, in SystemZTargetLowering()
6854 bool IsSigned = (Op->getOpcode() == ISD::SINT_TO_FP || in lower_INT_TO_FP()
7149 case ISD::SINT_TO_FP: in LowerOperation()
7308 case ISD::SINT_TO_FP: in LowerOperationWrapper()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp646 ISD::SETCC, ISD::SHL, ISD::SINT_TO_FP, ISD::SMAX, in NVPTXTargetLowering()
814 ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::SETCC}, in NVPTXTargetLowering()
925 {ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT}, in NVPTXTargetLowering()
929 {ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT}, in NVPTXTargetLowering()
2921 case ISD::SINT_TO_FP: in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVTargetTransformInfo.cpp1659 case ISD::SINT_TO_FP: in getCastInstrCost()
1661 unsigned IsSigned = ISD == ISD::SINT_TO_FP; in getCastInstrCost()

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