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Searched refs:SIGN_EXTEND_VECTOR_INREG (Results 1 – 15 of 15) sorted by relevance

/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h892 SIGN_EXTEND_VECTOR_INREG, enumerator
1764 Opcode == ISD::SIGN_EXTEND_VECTOR_INREG; in isExtVecInRegOpcode()
H A DSelectionDAG.h992 case ISD::SIGN_EXTEND_VECTOR_INREG:
1008 case ISD::SIGN_EXTEND_VECTOR_INREG:
1009 return ISD::SIGN_EXTEND_VECTOR_INREG;
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp80 case ISD::SIGN_EXTEND_VECTOR_INREG: in ScalarizeVectorResult()
521 case ISD::SIGN_EXTEND_VECTOR_INREG: in ScalarizeVecRes_VecInregOp()
1192 case ISD::SIGN_EXTEND_VECTOR_INREG: in SplitVectorResult()
3498 case ISD::SIGN_EXTEND_VECTOR_INREG: in SplitVectorOperand()
4859 case ISD::SIGN_EXTEND_VECTOR_INREG: in WidenVectorResult()
5461 return DAG.getNode(ISD::SIGN_EXTEND_VECTOR_INREG, DL, WidenVT, InOp); in WidenVecRes_Convert()
5614 case ISD::SIGN_EXTEND_VECTOR_INREG: in WidenVecRes_EXTEND_VECTOR_INREG()
5629 case ISD::SIGN_EXTEND_VECTOR_INREG: in WidenVecRes_EXTEND_VECTOR_INREG()
6823 case ISD::SIGN_EXTEND_VECTOR_INREG: in WidenVectorOperand()
6997 return DAG.getNode(ISD::SIGN_EXTEND_VECTOR_INREG, DL, VT, InOp); in WidenVecOp_EXTEND()
H A DSelectionDAGDumper.cpp397 case ISD::SIGN_EXTEND_VECTOR_INREG: return "sign_extend_vector_inreg"; in getOperationName()
H A DLegalizeVectorOps.cpp447 case ISD::SIGN_EXTEND_VECTOR_INREG: in LegalizeOp()
942 case ISD::SIGN_EXTEND_VECTOR_INREG: in Expand()
H A DSelectionDAG.cpp3122 case ISD::SIGN_EXTEND_VECTOR_INREG: in isSplatValue()
4055 case ISD::SIGN_EXTEND_VECTOR_INREG: { in computeKnownBits()
4873 case ISD::SIGN_EXTEND_VECTOR_INREG: { in ComputeNumSignBits()
5566 case ISD::SIGN_EXTEND_VECTOR_INREG: in canCreateUndefOrPoison()
6535 case ISD::SIGN_EXTEND_VECTOR_INREG: in getNode()
H A DTargetLowering.cpp902 case ISD::SIGN_EXTEND_VECTOR_INREG: in SimplifyMultipleUseDemandedBits()
2528 case ISD::SIGN_EXTEND_VECTOR_INREG: in SimplifyDemandedBits()
2537 bool IsVecInReg = Op.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG; in SimplifyDemandedBits()
3676 case ISD::SIGN_EXTEND_VECTOR_INREG: in SimplifyDemandedVectorElts()
H A DLegalizeIntegerTypes.cpp155 case ISD::SIGN_EXTEND_VECTOR_INREG: in PromoteIntegerResult()
6243 case ISD::SIGN_EXTEND_VECTOR_INREG: in PromoteIntRes_EXTEND_VECTOR_INREG()
H A DDAGCombiner.cpp1972 case ISD::SIGN_EXTEND_VECTOR_INREG: in visit()
13800 if (Opcode == ISD::SIGN_EXTEND || Opcode == ISD::SIGN_EXTEND_VECTOR_INREG) in tryToFoldExtendOfConstant()
14447 N0.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG) in visitSIGN_EXTEND()
14448 return DAG.getNode(ISD::SIGN_EXTEND_VECTOR_INREG, SDLoc(N), VT, in visitSIGN_EXTEND()
15063 N0.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG) in visitANY_EXTEND()
15633 TLI.isOperationLegal(ISD::SIGN_EXTEND_VECTOR_INREG, VT))) in visitSIGN_EXTEND_INREG()
15634 return DAG.getNode(ISD::SIGN_EXTEND_VECTOR_INREG, DL, VT, N00); in visitSIGN_EXTEND_INREG()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp311 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, T, Custom); in WebAssemblyTargetLowering()
1603 case ISD::SIGN_EXTEND_VECTOR_INREG: in ReplaceNodeResults()
1663 case ISD::SIGN_EXTEND_VECTOR_INREG: in LowerOperation()
2352 case ISD::SIGN_EXTEND_VECTOR_INREG: in LowerEXTEND_VECTOR_INREG()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp867 ISD::SIGN_EXTEND_VECTOR_INREG, in initActions()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp212 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, T, Legal); in initializeHVXLowering()
288 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, T, Legal); in initializeHVXLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp478 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Custom); in SystemZTargetLowering()
7122 case ISD::SIGN_EXTEND_VECTOR_INREG: in LowerOperation()
7602 } else if ((Opcode == ISD::SIGN_EXTEND_VECTOR_INREG || in combineExtract()
9031 (Op.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG || in detectEvenOddMultiplyOperand()
9033 bool IsSigned = Op.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG; in detectEvenOddMultiplyOperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp1283 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom); in X86TargetLowering()
1284 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom); in X86TargetLowering()
1285 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom); in X86TargetLowering()
1392 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Legal); in X86TargetLowering()
1631 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Custom); in X86TargetLowering()
1927 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Custom); in X86TargetLowering()
2678 ISD::SIGN_EXTEND_VECTOR_INREG, in X86TargetLowering()
4757 case ISD::SIGN_EXTEND_VECTOR_INREG: in getEXTEND_VECTOR_INREG()
6579 case ISD::SIGN_EXTEND_VECTOR_INREG: { in getFauxShuffleMask()
21374 Lo = DAG.getNode(ISD::SIGN_EXTEND_VECTOR_INREG, DL, MVT::v8i32, In); in LowerTruncateVecI1()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td485 def sext_invec : SDNode<"ISD::SIGN_EXTEND_VECTOR_INREG", SDTExtInvec>;