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Searched refs:SIGN_EXTEND_INREG (Results 1 – 25 of 41) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp126 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in R600TargetLowering()
128 setOperationAction(ISD::SIGN_EXTEND_INREG, {MVT::v2i1, MVT::v4i1}, Expand); in R600TargetLowering()
131 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); in R600TargetLowering()
132 setOperationAction(ISD::SIGN_EXTEND_INREG, {MVT::v2i8, MVT::v4i8}, Expand); in R600TargetLowering()
135 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); in R600TargetLowering()
136 setOperationAction(ISD::SIGN_EXTEND_INREG, {MVT::v2i16, MVT::v4i16}, Expand); in R600TargetLowering()
138 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); in R600TargetLowering()
139 setOperationAction(ISD::SIGN_EXTEND_INREG, {MVT::v2i32, MVT::v4i32}, Expand); in R600TargetLowering()
141 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Expand); in R600TargetLowering()
734 OVF = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, OVF, in LowerUADDSUBO()
[all …]
H A DAMDGPUISelLowering.cpp1376 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG); in LowerOperation()
1420 case ISD::SIGN_EXTEND_INREG: in ReplaceNodeResults()
2009 Div = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Div, InRegSize); in LowerDIVREM24()
2010 Rem = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Rem, InRegSize); in LowerDIVREM24()
3682 Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp); in LowerSIGN_EXTEND_INREG()
5194 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom, in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp132 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in BPFTargetLowering()
134 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); in BPFTargetLowering()
135 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); in BPFTargetLowering()
136 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Expand); in BPFTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaISelLowering.cpp61 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in XtensaTargetLowering()
62 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); in XtensaTargetLowering()
63 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); in XtensaTargetLowering()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h826 SIGN_EXTEND_INREG, enumerator
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp290 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in WebAssemblyTargetLowering()
295 setOperationAction(ISD::SIGN_EXTEND_INREG, T, Action); in WebAssemblyTargetLowering()
298 setOperationAction(ISD::SIGN_EXTEND_INREG, T, Expand); in WebAssemblyTargetLowering()
1423 case ISD::SIGN_EXTEND_INREG: in ReplaceNodeResults()
1482 case ISD::SIGN_EXTEND_INREG: in LowerOperation()
1940 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Op.getValueType(), NewExtract, in LowerSIGN_EXTEND_INREG()
2087 if (IndexExt->getOpcode() != ISD::SIGN_EXTEND_INREG) in LowerBUILD_VECTOR()
2384 ShiftedValue = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, in unrollVectorShift()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelDAGToDAG.cpp291 if (N.getOpcode() == ISD::SIGN_EXTEND_INREG && in selectSExti32()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp167 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Custom); in ARCTargetLowering()
796 case ISD::SIGN_EXTEND_INREG: in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp130 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in LanaiTargetLowering()
131 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); in LanaiTargetLowering()
132 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); in LanaiTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp632 if (isInt<32>(Val) && N0.getOpcode() == ISD::SIGN_EXTEND_INREG && in tryShrinkShlLogicImm()
730 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) { in trySignedBitfieldExtract()
1191 if (N0.getOpcode() != ISD::SIGN_EXTEND_INREG || !N0.hasOneUse()) in Select()
1286 X.getOpcode() == ISD::SIGN_EXTEND_INREG && in Select()
1313 X.getOpcode() == ISD::SIGN_EXTEND_INREG && in Select()
2883 if (N.getOpcode() == ISD::SIGN_EXTEND_INREG && in selectSExtBits()
3106 Node->getOpcode() == ISD::SIGN_EXTEND_INREG || in hasAllNBitUsers()
H A DRISCVISelLowering.cpp272 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in RISCVTargetLowering()
277 setOperationAction(ISD::SIGN_EXTEND_INREG, {MVT::i8, MVT::i16}, Expand); in RISCVTargetLowering()
1459 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Legal); in RISCVTargetLowering()
1460 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal); in RISCVTargetLowering()
1489 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG); in RISCVTargetLowering()
5735 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i64, WideOp, in lowerSADDO_SSUBO()
5751 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i64, Mul, in lowerSMULO()
12182 SDValue NewRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i64, NewWOp, in customLegalizeToWOpWithSExt()
12395 // Custom legalize ISD::SHL by placing a SIGN_EXTEND_INREG after. This is in ReplaceNodeResults()
12405 SDValue NewRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, D in ReplaceNodeResults()
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp118 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in MSP430TargetLowering()
989 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT, Victim, in LowerShifts()
1238 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT, in LowerSIGN_EXTEND()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp110 case ISD::SIGN_EXTEND_INREG: in PromoteIntegerResult()
924 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, in PromoteIntRes_INT_EXTEND()
1295 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, in PromoteIntRes_SADDSUBO()
1416 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), in PromoteIntRes_SIGN_EXTEND_INREG()
1827 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(), in PromoteIntRes_XMULO()
2316 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), in PromoteIntOp_SIGN_EXTEND()
2817 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break; in ExpandIntegerResult()
4834 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi, in ExpandIntRes_SIGN_EXTEND()
4848 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo, in ExpandIntRes_SIGN_EXTEND_INREG()
4860 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi, in ExpandIntRes_SIGN_EXTEND_INREG()
H A DSelectionDAGDumper.cpp378 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg"; in getOperationName()
H A DLegalizeVectorOps.cpp431 case ISD::SIGN_EXTEND_INREG: in LegalizeOp()
857 case ISD::SIGN_EXTEND_INREG: in Expand()
H A DLegalizeDAG.cpp750 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, in LegalizeLoadOps()
928 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, in LegalizeLoadOps()
1028 case ISD::SIGN_EXTEND_INREG: { in LegalizeOp()
3190 RHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, OuterType, in ExpandNode()
3221 if (RHS->getOpcode() == ISD::SIGN_EXTEND_INREG && in ExpandNode()
3365 case ISD::SIGN_EXTEND_INREG: { in ExpandNode()
H A DDAGCombiner.cpp1466 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) in SExtPromoteOperand()
1478 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, NewOp.getValueType(), NewOp, in SExtPromoteOperand()
1913 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); in visit()
3199 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) { in visitADDLikeCommutative()
4046 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) { in visitSUB()
5781 (HandOpcode == ISD::SIGN_EXTEND_INREG && in hoistLogicOpWithSameOpcodeHands()
5803 if (HandOpcode == ISD::SIGN_EXTEND_INREG) in hoistLogicOpWithSameOpcodeHands()
10949 Opc0 != ISD::SIGN_EXTEND_INREG)) { in foldABSToABD()
10960 if (Opc0 == ISD::SIGN_EXTEND_INREG) { in foldABSToABD()
11011 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) { in visitABS()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp282 setOperationAction(ISD::SIGN_EXTEND_INREG, T, Custom); in initializeHVXLowering()
401 setOperationAction(ISD::SIGN_EXTEND_INREG, T, Legal); in initializeHVXLowering()
404 setOperationAction(ISD::SIGN_EXTEND_INREG, T, Legal); in initializeHVXLowering()
1690 Elems[i] = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NTy, in LowerHvxConcatVectors()
2946 case ISD::SIGN_EXTEND_INREG: in SplitVectorOp()
3187 case ISD::SIGN_EXTEND_INREG: in LowerHvxOperation()
H A DHexagonISelDAGToDAG.cpp1610 case ISD::SIGN_EXTEND_INREG: { in DetectUseSxtw()
1678 case ISD::SIGN_EXTEND_INREG: in keepsLowBits()
1754 if (N->getOpcode() == ISD::SIGN_EXTEND_INREG) { in isPositiveHalfWord()
H A DHexagonISelLowering.cpp1517 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in HexagonTargetLowering()
1703 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Legal); in HexagonTargetLowering()
1704 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Legal); in HexagonTargetLowering()
1705 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal); in HexagonTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp556 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i64, Legal); in NVPTXTargetLowering()
557 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); in NVPTXTargetLowering()
558 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal); in NVPTXTargetLowering()
559 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); in NVPTXTargetLowering()
560 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in NVPTXTargetLowering()
561 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Expand); in NVPTXTargetLowering()
5629 Op.getOpcode() == ISD::SIGN_EXTEND_INREG) { in IsMulWideOperandDemotable()
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1668 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); in SparcTargetLowering()
1669 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); in SparcTargetLowering()
1670 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); in SparcTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp260 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in PPCTargetLowering()
583 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in PPCTargetLowering()
882 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand); in PPCTargetLowering()
1320 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Legal); in PPCTargetLowering()
1321 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Legal); in PPCTargetLowering()
1322 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Legal); in PPCTargetLowering()
1323 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Legal); in PPCTargetLowering()
1324 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Legal); in PPCTargetLowering()
1325 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal); in PPCTargetLowering()
1326 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal); in PPCTargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp807 N.getOpcode() == ISD::SIGN_EXTEND_INREG) { in getExtendTypeForNode()
809 if (N.getOpcode() == ISD::SIGN_EXTEND_INREG) in getExtendTypeForNode()
2536 assert(N->getOpcode() == ISD::SIGN_EXTEND_INREG); in isBitfieldExtractOpFromSExtInReg()
2716 case ISD::SIGN_EXTEND_INREG: in isBitfieldExtractOp()
4609 case ISD::SIGN_EXTEND_INREG: in Select()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp202 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand); in addTypeForNEON()
428 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Legal); in addMVEVectorTypes()
429 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Legal); in addMVEVectorTypes()
430 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Legal); in addMVEVectorTypes()
431 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v8i8, Legal); in addMVEVectorTypes()
432 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v8i16, Legal); in addMVEVectorTypes()
1035 ISD::SIGN_EXTEND_INREG, ISD::STORE, ISD::SIGN_EXTEND, ISD::ZERO_EXTEND, in ARMTargetLowering()
1404 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); in ARMTargetLowering()
1405 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); in ARMTargetLowering()
1407 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in ARMTargetLowering()
[all …]

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