Home
last modified time | relevance | path

Searched refs:SHL_VL (Results 1 – 3 of 3) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h241 SHL_VL, enumerator
H A DRISCVISelLowering.cpp4848 Interleaved = DAG.getNode(RISCVISD::SHL_VL, DL, WideContainerVT, in getWideningInterleave()
14427 case RISCVISD::SHL_VL: in getZExtOpcode()
14637 case RISCVISD::SHL_VL: in isSupportedRoot()
14727 case RISCVISD::SHL_VL: in isCommutative()
14944 case RISCVISD::SHL_VL: in getSupportedFoldings()
17248 case RISCVISD::SHL_VL: in PerformDAGCombine()
20480 NODE_NAME_CASE(SHL_VL) in getTargetNodeName()
H A DRISCVInstrInfoVVLPatterns.td110 def riscv_shl_vl : SDNode<"RISCVISD::SHL_VL", SDT_RISCVIntBinOp_VL>;