| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 791 SHL_PARTS, enumerator
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 121 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); in LanaiTargetLowering()
192 case ISD::SHL_PARTS: in LowerOperation()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 111 setOperationAction(ISD::SHL_PARTS, MVT::i8, Expand); in MSP430TargetLowering()
112 setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand); in MSP430TargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 353 case ISD::SHL_PARTS: return "shl_parts"; in getOperationName()
|
| H A D | SelectionDAG.cpp | 3648 case ISD::SHL_PARTS: in computeKnownBits()
3663 if (Opcode == ISD::SHL_PARTS) in computeKnownBits()
10314 case ISD::SHL_PARTS: in getNode()
|
| H A D | LegalizeDAG.cpp | 1282 case ISD::SHL_PARTS: { in LegalizeOp()
|
| H A D | LegalizeIntegerTypes.cpp | 4704 PartsOpc = ISD::SHL_PARTS; in ExpandIntRes_Shift()
|
| H A D | TargetLowering.cpp | 8124 bool IsSHL = Node->getOpcode() == ISD::SHL_PARTS; in expandShiftParts()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.cpp | 112 setOperationAction(ISD::SHL_PARTS, VT, Expand); in BPFTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelLowering.cpp | 153 setOperationAction({ISD::SHL_PARTS, ISD::SRL_PARTS, ISD::SRA_PARTS}, MVT::i32, in R600TargetLowering()
403 case ISD::SHL_PARTS: in LowerOperation()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 64 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); in CSKYTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 563 setOperationAction(ISD::SHL_PARTS, MVT::i32 , Custom); in NVPTXTargetLowering()
566 setOperationAction(ISD::SHL_PARTS, MVT::i64 , Custom); in NVPTXTargetLowering()
2493 assert(Op.getOpcode() == ISD::SHL_PARTS); in LowerShiftLeftParts()
2779 case ISD::SHL_PARTS: in LowerOperation()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 103 for (auto OP : {ISD::SHL_PARTS, ISD::SRA_PARTS, ISD::SRL_PARTS}) in M68kTargetLowering()
1416 case ISD::SHL_PARTS: in LowerOperation()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 390 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); in MipsTargetLowering()
396 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); in MipsTargetLowering()
1258 case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG); in LowerOperation()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1827 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); in SparcTargetLowering()
1861 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand); in SparcTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 100 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); in XCoreTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 94 setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand); in AVRTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 157 ISD::SDIVREM, ISD::UDIVREM, ISD::SHL_PARTS, ISD::SRA_PARTS, in WebAssemblyTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 77 setOperationAction(ISD::SHL_PARTS, GRLenVT, Custom); in LoongArchTargetLowering()
396 case ISD::SHL_PARTS: in LowerOperation()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 170 setOperationAction(ISD::SHL_PARTS, IntVT, Expand); in initSPUActions()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1602 ISD::SHL_PARTS, ISD::SRA_PARTS, ISD::SRL_PARTS, in HexagonTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 346 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand); in SystemZTargetLowering()
352 setOperationAction(ISD::SHL_PARTS, MVT::i128, Expand); in SystemZTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 1175 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); in ARMTargetLowering()
1192 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); in ARMTargetLowering()
6377 assert(Op.getOpcode() == ISD::SHL_PARTS); in LowerShiftLeftParts()
10607 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG); in LowerOperation()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 749 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); in PPCTargetLowering()
754 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); in PPCTargetLowering()
11845 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG); in LowerOperation()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 336 setOperationAction({ISD::SHL_PARTS, ISD::SRL_PARTS, ISD::SRA_PARTS}, XLenVT, in RISCVTargetLowering()
6277 case ISD::SHL_PARTS: in LowerOperation()
|