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Searched refs:SGPR0 (Results 1 – 6 of 6) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallingConv.td72 SGPR0, SGPR1, SGPR2, SGPR3, SGPR4, SGPR5, SGPR6, SGPR7,
105 SGPR0, SGPR1, SGPR2, SGPR3, SGPR4, SGPR5, SGPR6, SGPR7,
194 !foreach(i, !range(0, 30), !cast<Register>("SGPR"#i)) // SGPR0-29
H A DSIMachineFunctionInfo.cpp570 return AMDGPU::SGPR0 + NumUserSGPRs; in getNextUserSGPR()
574 return AMDGPU::SGPR0 + NumUserSGPRs + NumSystemSGPRs; in getNextSystemSGPR()
592 Register GitPtrLo = AMDGPU::SGPR0; // Low GIT address passed in in getGITPtrLoReg()
H A DSIInsertWaitcnts.cpp104 unsigned SGPR0; member
758 assert(Reg >= Encoding.SGPR0 && Reg < SQ_MAX_PGM_SGPRS); in getRegInterval()
759 Result.first = Reg - Encoding.SGPR0 + NUM_ALL_VGPRS; in getRegInterval()
2450 Encoding.SGPR0 = in runOnMachineFunction()
2451 TRI->getEncodingValue(AMDGPU::SGPR0) & AMDGPU::HWEncoding::REG_IDX_MASK; in runOnMachineFunction()
2452 Encoding.SGPRL = Encoding.SGPR0 + NumSGPRsMax - 1; in runOnMachineFunction()
H A DSOPInstructions.td1085 // SCC = S_CMPK_EQ_I32 SGPR0, imm
H A DSIInstrInfo.cpp759 bool AlignedDest = ((DestSubReg - AMDGPU::SGPR0) % 2) == 0; in expandSGPRCopy()
760 bool AlignedSrc = ((SrcSubReg - AMDGPU::SGPR0) % 2) == 0; in expandSGPRCopy()
H A DSIISelLowering.cpp77 if (!CCInfo.isAllocated(AMDGPU::SGPR0 + Reg)) { in findFirstFreeSGPR()
78 return AMDGPU::SGPR0 + Reg; in findFirstFreeSGPR()