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Searched refs:SGPR (Results 1 – 18 of 18) sorted by relevance

/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsAMDGPU.td200 // Set EXEC according to a thread count packed in an SGPR input:
206 [llvm_i32_ty, // 32-bit SGPR input
860 [llvm_v8i32_ty], // rsrc(SGPR)
861 !if(P_.IsSample, [llvm_v4i32_ty, // samp(SGPR)
1097 [llvm_v4i32_ty, // rsrc(SGPR)
1126 [llvm_v4i32_ty, // rsrc(SGPR)
1128 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
1143 [llvm_v4i32_ty, // rsrc(SGPR)
1145 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
1156 [AMDGPUBufferRsrcTy, // rsrc(SGPR)
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.td340 // SGPR registers
342 defm SGPR#Index :
389 (add (sequence "SGPR%u_LO16", 0, 105))> {
397 (add (sequence "SGPR%u_HI16", 0, 105))> {
404 // SGPR 32-bit registers
406 (add (sequence "SGPR%u", 0, 105))> {
407 // Give all SGPR classes higher priority than VGPR classes, because
414 // SGPR 64-bit registers
417 // SGPR 96-bit registers.
420 // SGPR 128-bit registers
[all …]
H A DAMDGPUCallingConv.td158 (sequence "SGPR%u", 30, 105)
162 (add (sequence "SGPR%u", 4, 31), (sequence "SGPR%u", 64, 105))
194 !foreach(i, !range(0, 30), !cast<Register>("SGPR"#i)) // SGPR0-29
229 !foreach(i, !range(105), !cast<Register>("SGPR"#i))
255 (add (sequence "SGPR%u", 0, 105), VCC_LO, VCC_HI)
H A DAMDGPURegisterBanks.td9 def SGPRRegBank : RegisterBank<"SGPR",
H A DSMInstructions.td575 // The alternative GFX9 SGPR encoding using soffset to encode the
577 // encoding family to avoid conflicts with the primary SGPR variant.
898 // 3. SGPR offset
910 // 4. SGPR+IMM offset
956 // 3. Offset loaded in an 32bit SGPR
968 // 4. Offset as an 32-bit SGPR + immediate
986 // 2. SGPR offset
993 // 3. SGPR+IMM offset
1017 // 2. Offset as an 32-bit SGPR
1024 // 3. Offset as an 32-bit SGPR + immediate
H A DSIFrameLowering.cpp73 MachineFunction &MF, LiveRegUnits &LiveUnits, Register SGPR, in getVGPRSpillLaneOrTempRegister() argument
103 SGPR, PrologEpilogSGPRSaveRestoreInfo( in getVGPRSpillLaneOrTempRegister()
107 dbgs() << printReg(SGPR, TRI) << " requires fallback spill to " in getVGPRSpillLaneOrTempRegister()
116 SGPR, in getVGPRSpillLaneOrTempRegister()
119 << printReg(SGPR, TRI) << '\n'); in getVGPRSpillLaneOrTempRegister()
123 SGPR, PrologEpilogSGPRSaveRestoreInfo( in getVGPRSpillLaneOrTempRegister()
126 LLVM_DEBUG(dbgs() << "Saving " << printReg(SGPR, TRI) << " with copy to " in getVGPRSpillLaneOrTempRegister()
H A DAMDGPUGenRegisterBankInfo.def61 {0, 1, SGPRRegBank}, // SGPR begin
H A DAMDGPU.td178 "VI SGPR initialization bug requiring a fixed SGPR allocation size"
208 …"VMEM instruction followed by scalar writing to EXEC mask, M0 or SGPR leads to incorrect execution…
271 "Negative immediate offsets in scratch instructions with an SGPR offset page fault on GFX9"
517 "Support SGPR for Src1 of DPP instructions"
842 "V_CMPX does not write VCC/SGPR in addition to EXEC"
H A DSIRegisterInfo.h75 /// Return the largest available SGPR aligned to \p Align for the register
165 MachineBasicBlock &RestoreMBB, Register SGPR,
197 /// \returns true if this class contains only SGPR registers in isSGPRClassID()
202 /// \returns true if this class ID contains only SGPR registers
224 /// \returns true only if this class contains both VGPR and SGPR registers in hasVGPRs()
239 /// \returns true if this class contains SGPR registers. in hasVectorRegisters()
257 /// \returns A SGPR reg class with the same width as \p SRC
H A DSIInstrInfo.td102 SDTCisVT<4, i32>, // soffset(SGPR)
120 SDTCisVT<4, i32>, // soffset(SGPR)
138 SDTCisVT<4, i32>, // soffset(SGPR)
176 SDTCisVT<4, i32>, // soffset(SGPR)
202 SDTCisVT<5, i32>, // soffset(SGPR)
241 SDTCisVT<6, i32>, // soffset(SGPR)
H A DVOP3Instructions.td466 // is in an SGPR (uniform values can end up in VGPRs as well).
489 // FIXME: With unlucky SGPR operands, we could penalize code by
490 // blocking folding SGPR->VGPR copies later.
780 // GISel-specific pattern that avoids creating a SGPR->VGPR copy if
H A DSIInstrFormats.td49 // Combined SGPR/VGPR spill bit
H A DSIInstrInfo.cpp4953 if (llvm::all_of(SGPRsUsed, [this, SGPRUsed](unsigned SGPR) { in verifyInstruction() argument
4954 return !RI.regsOverlap(SGPRUsed, SGPR); in verifyInstruction()
5755 RegSubRegPair SGPR(Op.getReg(), Op.getSubReg()); in isOperandLegal() local
5756 if (!SGPRsUsed.count(SGPR) && in isOperandLegal()
5761 SGPRsUsed.insert(SGPR); in isOperandLegal()
6082 Register SGPR = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass); in readlaneVGPRToSGPR() local
6084 get(AMDGPU::V_READFIRSTLANE_B32), SGPR) in readlaneVGPRToSGPR()
6086 SRegs.push_back(SGPR); in readlaneVGPRToSGPR()
6108 Register SGPR = readlaneVGPRToSGPR(SBase->getReg(), MI, MRI); in legalizeOperandsSMRD() local
6109 SBase->setReg(SGPR); in legalizeOperandsSMRD()
[all …]
H A DVOPInstructions.td443 bits<10> vdst; // VGPR or AGPR, but not SGPR. vdst{8} is not encoded in the instruction.
538 // than VGPRs (at most 1 can be an SGPR);
541 // replaces OMOD and the dest fields with SD and SDST (SGPR destination)
H A DVOP2Instructions.td542 // Write out to vcc or arbitrary SGPR.
567 // Write out to vcc or arbitrary SGPR and read in from vcc or
568 // arbitrary SGPR.
611 // Read in from vcc or arbitrary SGPR.
H A DSIRegisterInfo.cpp1965 Register SGPR, RegScavenger *RS) const { in spillEmergencySGPR() argument
1966 SGPRSpillBuilder SB(*this, *ST.getInstrInfo(), isWave32, MI, SGPR, false, 0, in spillEmergencySGPR()
H A DSIInstructions.td1582 // FIXME: Make SGPR
2608 // comparisons may write to a pair of SGPRs or a single SGPR, so treat
2609 // these as 32 or 64-bit comparisons. When legalizing SGPR copies,
H A DSOPInstructions.td413 // is not an SGPR number.