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Searched refs:SGPR (Results 1 – 21 of 21) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallingConv.td26 !foreach(i, !range(4, 30), !cast<Register>("SGPR"#i)) // SGPR4-29
50 !foreach(i, !range(0, 44), !cast<Register>("SGPR"#i)) // SGPR0-43
62 !foreach(i, !range(0, 44), !cast<Register>("SGPR"#i)) // SGPR0-43
98 (add (sequence "SGPR%u", 30, 39),
99 (sequence "SGPR%u", 48, 55),
100 (sequence "SGPR%u", 64, 71),
101 (sequence "SGPR%u", 80, 87),
102 (sequence "SGPR%u", 96, 105))
106 (add (sequence "SGPR%u", 4, 31), (sequence "SGPR%u", 64, 105))
138 !foreach(i, !range(0, 30), !cast<Register>("SGPR"#i)) // SGPR0-29
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H A DSIRegisterInfo.td303 // SGPR registers
305 defm SGPR#Index :
355 (add (sequence "SGPR%u_LO16", 0, 105))> {
363 (add (sequence "SGPR%u_HI16", 0, 105))> {
370 // SGPR 32-bit registers
372 (add (sequence "SGPR%u", 0, 105))> {
373 // Give all SGPR classes higher priority than VGPR classes, because
380 // SGPR 64-bit registers
383 // SGPR 96-bit registers.
386 // SGPR 128-bit registers
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H A DGCNRegPressure.h32 enum RegKind { SGPR, VGPR, AGPR, TOTAL_KINDS }; enumerator
38 bool empty() const { return !Value[SGPR] && !Value[VGPR] && !Value[AGPR]; } in empty()
43 unsigned getSGPRNum() const { return Value[SGPR]; } in getSGPRNum()
70 unsigned getSGPRTuplesWeight() const { return Value[TOTAL_KINDS + SGPR]; } in getSGPRTuplesWeight()
H A DAMDGPURegisterBanks.td9 def SGPRRegBank : RegisterBank<"SGPR",
H A DSMInstructions.td579 // The alternative GFX9 SGPR encoding using soffset to encode the
581 // encoding family to avoid conflicts with the primary SGPR variant.
902 // 3. SGPR offset
914 // 4. SGPR+IMM offset
960 // 3. Offset loaded in an 32bit SGPR
972 // 4. Offset as an 32-bit SGPR + immediate
990 // 2. SGPR offset
997 // 3. SGPR+IMM offset
1021 // 2. Offset as an 32-bit SGPR
1028 // 3. Offset as an 32-bit SGPR + immediate
H A DSIFrameLowering.cpp73 MachineFunction &MF, LiveRegUnits &LiveUnits, Register SGPR, in getVGPRSpillLaneOrTempRegister() argument
103 SGPR, PrologEpilogSGPRSaveRestoreInfo( in getVGPRSpillLaneOrTempRegister()
107 dbgs() << printReg(SGPR, TRI) << " requires fallback spill to " in getVGPRSpillLaneOrTempRegister()
116 SGPR, in getVGPRSpillLaneOrTempRegister()
119 << printReg(SGPR, TRI) << '\n'); in getVGPRSpillLaneOrTempRegister()
123 SGPR, PrologEpilogSGPRSaveRestoreInfo( in getVGPRSpillLaneOrTempRegister()
126 LLVM_DEBUG(dbgs() << "Saving " << printReg(SGPR, TRI) << " with copy to " in getVGPRSpillLaneOrTempRegister()
H A DAMDGPUGenRegisterBankInfo.def61 {0, 1, SGPRRegBank}, // SGPR begin
H A DSIRegisterInfo.h193 MachineBasicBlock &RestoreMBB, Register SGPR,
H A DAMDGPU.td208 "VI SGPR initialization bug requiring a fixed SGPR allocation size"
238 …"VMEM instruction followed by scalar writing to EXEC mask, M0 or SGPR leads to incorrect execution…
307 "Negative immediate offsets in scratch instructions with an SGPR offset page fault on GFX9"
650 "Support SGPR for Src1 of DPP instructions"
1001 "V_CMPX does not write VCC/SGPR in addition to EXEC"
H A DVOPDInstructions.td176 // limited to VCC src2 only, and a real SGPR will be used as an operand
H A DSIInstrInfo.td105 SDTCisVT<4, i32>, // soffset(SGPR)
123 SDTCisVT<4, i32>, // soffset(SGPR)
141 SDTCisVT<4, i32>, // soffset(SGPR)
179 SDTCisVT<4, i32>, // soffset(SGPR)
205 SDTCisVT<5, i32>, // soffset(SGPR)
244 SDTCisVT<6, i32>, // soffset(SGPR)
1809 // Returns the register class to use for source VGPR, SGPR or inline constant
H A DSIInstrInfo.cpp5138 if (llvm::all_of(SGPRsUsed, [this, SGPRUsed](unsigned SGPR) { in verifyInstruction() argument
5139 return !RI.regsOverlap(SGPRUsed, SGPR); in verifyInstruction()
6060 RegSubRegPair SGPR(Op.getReg(), Op.getSubReg()); in isOperandLegal() local
6061 if (!SGPRsUsed.count(SGPR) && in isOperandLegal()
6066 SGPRsUsed.insert(SGPR); in isOperandLegal()
6384 Register SGPR = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass); in readlaneVGPRToSGPR() local
6386 get(AMDGPU::V_READFIRSTLANE_B32), SGPR) in readlaneVGPRToSGPR()
6388 SRegs.push_back(SGPR); in readlaneVGPRToSGPR()
6410 Register SGPR = readlaneVGPRToSGPR(SBase->getReg(), MI, MRI); in legalizeOperandsSMRD() local
6411 SBase->setReg(SGPR); in legalizeOperandsSMRD()
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H A DSIInstrFormats.td49 // Combined SGPR/VGPR spill bit
H A DVOPInstructions.td253 // the same for SGPR, imm, and VGPR_32 whether the instruction is True16 or not.
510 bits<10> vdst; // VGPR or AGPR, but not SGPR. vdst{8} is not encoded in the instruction.
666 // than VGPRs (at most 1 can be an SGPR);
669 // replaces OMOD and the dest fields with SD and SDST (SGPR destination)
H A DGCNRegPressure.cpp41 return STI->isSGPRClass(RC) ? SGPR : (STI->isAGPRClass(RC) ? AGPR : VGPR); in getRegKind()
H A DVOP3Instructions.td537 // is in an SGPR (uniform values can end up in VGPRs as well).
560 // FIXME: With unlucky SGPR operands, we could penalize code by
561 // blocking folding SGPR->VGPR copies later.
897 // GISel-specific pattern that avoids creating a SGPR->VGPR copy if
H A DVOP2Instructions.td653 // Write out to vcc or arbitrary SGPR.
678 // Write out to vcc or arbitrary SGPR and read in from vcc or
679 // arbitrary SGPR.
722 // Read in from vcc or arbitrary SGPR.
H A DSIRegisterInfo.cpp2242 Register SGPR, RegScavenger *RS) const { in spillEmergencySGPR() argument
2243 SGPRSpillBuilder SB(*this, *ST.getInstrInfo(), isWave32, MI, SGPR, false, 0, in spillEmergencySGPR()
H A DSIInstructions.td2176 // unnecessary copy from SGPR to VGPR.
2808 // comparisons may write to a pair of SGPRs or a single SGPR, so treat
2809 // these as 32 or 64-bit comparisons. When legalizing SGPR copies,
H A DSOPInstructions.td414 // is not an SGPR number.
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsAMDGPU.td216 // Set EXEC according to a thread count packed in an SGPR input:
222 [llvm_i32_ty, // 32-bit SGPR input
1081 [llvm_any_ty], // rsrc(SGPR); Valid types: v4i32 and v8i32
1082 !if(P_.IsSample, [llvm_any_ty, // samp(SGPR);
1331 [llvm_v4i32_ty, // rsrc(SGPR)
1360 [llvm_v4i32_ty, // rsrc(SGPR)
1362 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
1377 [llvm_v4i32_ty, // rsrc(SGPR)
1379 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
1390 [AMDGPUBufferRsrcTy, // rsrc(SGPR)
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