Searched refs:SExtOp (Results 1 – 4 of 4) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerCombiner.cpp | 511 Register SExtOp = in matchExtMulToMULL() local
513 if (KB->computeNumSignBits(SExtOp) > EltSize / 2) { in matchExtMulToMULL()
515 get<1>(MatchInfo) = IsSExt1 ? I1->getOperand(1).getReg() : SExtOp; in matchExtMulToMULL()
516 get<2>(MatchInfo) = IsSExt1 ? SExtOp : I2->getOperand(1).getReg(); in matchExtMulToMULL()
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| /freebsd/contrib/llvm-project/clang/lib/CIR/Lowering/DirectToLLVM/ |
| H A D | LowerToLLVM.cpp | 92 return bld.create<mlir::LLVM::SExtOp>(loc, dstTy, src); in createIntCast()
187 return rewriter.create<mlir::LLVM::SExtOp>(loc, llvmDstIntTy, llvmSrc); in getLLVMIntCast()
2241 rewriter.replaceOpWithNewOp<mlir::LLVM::SExtOp>( in matchAndRewrite()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVTargetTransformInfo.cpp | 1587 unsigned SExtOp[] = {RISCV::VSEXT_VF2, RISCV::VSEXT_VF4, RISCV::VSEXT_VF8}; in getCastInstrCost() local
1590 (ISD == ISD::SIGN_EXTEND) ? SExtOp[PowDiff - 1] : ZExtOp[PowDiff - 1]; in getCastInstrCost()
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| H A D | RISCVISelLowering.cpp | 16429 SDValue SExtOp = DAG.getNode(ISD::SIGN_EXTEND_INREG, N, OpVT, in performSETCCCombine() local
16431 return DAG.getSetCC(dl, VT, SExtOp, DAG.getConstant(C1.trunc(32).sext(64), in performSETCCCombine()
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