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Searched refs:SETUNE (Results 1 – 25 of 41) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchFloat64InstrInfo.td182 def : PatFPSetcc<SETUNE, FCMP_CUNE_D, FPR64>;
194 defm : PatFPBrcond<SETUNE, FCMP_CUNE_D, FPR64>;
208 def : PatStrictFsetccs<SETUNE, FCMP_SUNE_D, FPR64>;
227 def : PatFPSelectcc<SETUNE, FCMP_CUNE_D, FSEL_xD, FPR64>;
H A DLoongArchFloat32InstrInfo.td206 def : PatFPSetcc<SETUNE, FCMP_CUNE_S, FPR32>;
226 defm : PatFPBrcond<SETUNE, FCMP_CUNE_S, FPR32>;
243 def : PatStrictFsetccs<SETUNE, FCMP_SUNE_S, FPR32>;
266 def : PatFPSelectcc<SETUNE, FCMP_CUNE_S, FSEL_xS, FPR32>;
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1701 SETUNE, // 1 1 1 0 True if unordered or not equal enumerator
1737 return Code == SETOEQ || Code == SETONE || Code == SETUEQ || Code == SETUNE; in isFPEqualitySetCC()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfoF2.td377 defm : BRCond_Bin_F2<SETUNE, "f2FCMPNE", BT32, BF32, MVC32>;
420 def : Pat<(brcond (i32 (setcc FPR32Op:$rs1, fpimm0, SETUNE)), bb:$imm16),
422 def : Pat<(i32 (setcc FPR32Op:$rs1, fpimm0, SETUNE)),
424 def : Pat<(select (i32 (setcc FPR32Op:$rs1, fpimm0, SETUNE)), FPR32Op:$rx, FPR32Op:$false),
H A DCSKYInstrInfoF1.td357 defm : BRCond_Bin<SETUNE, "FCMPNE", BT32, BF32, MVC32>;
392 def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETUNE)), bb:$imm16),
394 def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETUNE)),
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DAnalysis.cpp215 case FCmpInst::FCMP_UNE: return ISD::SETUNE; in getFCmpCondCode()
224 case ISD::SETONE: case ISD::SETUNE: return ISD::SETNE; in getFCmpCodeWithoutNaN()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.h127 case ISD::SETUNE: in fpCondCode2Fcc()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructions.td362 def COND_UNE : PatFrag<(ops), (OtherVT SETUNE)>;
370 def COND_UNE_NE : PatFrags<(ops), [(OtherVT SETUNE), (OtherVT SETNE)]>;
386 def COND_NE : PatFrags<(ops), [(OtherVT SETNE), (OtherVT SETUNE)]>;
H A DSIWholeQuadMode.cpp840 case ISD::SETUNE: in lowerKillF32()
H A DR600ISelLowering.cpp902 case ISD::SETUNE: in LowerSELECT_CC()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrFloat.td85 defm NE : ComparisonFP<SETUNE, "ne ", 0x5c, 0x62>;
H A DWebAssemblyInstrSIMD.td780 defm NE : SIMDConditionFP<"ne", SETUNE, 66>;
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp53 case ISD::SETUNE: in ISDCCtoARCCC()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp537 case ISD::SETUNE: return "setune"; in getOperationName()
H A DTargetLowering.cpp340 case ISD::SETUNE: in softenSetCCOperands()
5452 case ISD::SETUNE: NewCond = IsNegInf ? ISD::SETUGT : ISD::SETULT; break; in SimplifySetCC()
8917 ISD::CondCode OrderedCmpOpcode = IsInvertedFP ? ISD::SETUNE : ISD::SETOEQ; in expandIS_FPCLASS()
12165 if (isCondCodeLegal(ISD::SETUNE, OpVT)) { in LegalizeSetCCCondCode()
12166 CC1 = ISD::SETUNE; in LegalizeSetCCCondCode()
12167 CC2 = ISD::SETUNE; in LegalizeSetCCCondCode()
12203 case ISD::SETUNE: in LegalizeSetCCCondCode()
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp842 case ISD::SETUNE: in IntCondCCodeToICC()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp4297 case ISD::SETUNE: in getPredicateForSetCC()
4338 case ISD::SETUNE: in getCRIdxForSetCC()
4375 case ISD::SETUNE: CC = ISD::SETOEQ; Negate = true; break; in getVCmpInst()
4419 case ISD::SETUNE: CC = ISD::SETUEQ; Negate = true; break; in getVCmpInst()
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td921 def SETUNE : CondCode<"FCMP_UNE">;
1598 (setcc node:$lhs, node:$rhs, SETUNE)>;
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaISelLowering.cpp847 case ISD::SETUNE: in getFPBranchKind()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp404 case ISD::SETUNE: in getPTXCmpMode()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp354 setCondCodeAction(ISD::SETUNE, MVT::v64f16, Expand); in initializeHVXLowering()
369 setCondCodeAction(ISD::SETUNE, MVT::v32f32, Expand); in initializeHVXLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SVEInstrInfo.td2182 defm FCMNE_PPzZZ : sve_fp_3op_p_pd_cc<0b011, "fcmne", SETUNE, SETNE, SETUNE, SETNE>;
2192 defm FCMNE_PPzZ0 : sve_fp_2op_p_pd<0b110, "fcmne", SETUNE, SETNE, SETUNE, SETNE>;
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVSDPatterns.td1382 defm : VPatFPSetCCSDNode_VV_VF_FV<SETUNE, "PseudoVMFNE", "PseudoVMFNE">;
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsMSAInstrInfo.td152 def vfsetune_v4f32 : vfsetcc_type<v4i32, v4f32, SETUNE>;
153 def vfsetune_v2f64 : vfsetcc_type<v2i64, v2f64, SETUNE>;
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1830 case ISD::SETUNE: in TranslateM68kCC()

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