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Searched refs:SETOLT (Results 1 – 25 of 45) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchFloat64InstrInfo.td171 // SETOLT/SETOLE/SETULT/SETULE/SETLE/SETEQ/SETLT.
174 def : PatFPSetcc<SETOLT, FCMP_CLT_D, FPR64>;
187 defm : PatFPBrcond<SETOLT, FCMP_CLT_D, FPR64>;
201 def : PatStrictFsetccs<SETOLT, FCMP_SLT_D, FPR64>;
220 def : PatFPSelectcc<SETOLT, FCMP_CLT_D, FSEL_xD, FPR64>;
H A DLoongArchFloat32InstrInfo.td195 // SETOLT/SETOLE/SETULT/SETULE/SETLE/SETEQ/SETLT.
198 def : PatFPSetcc<SETOLT, FCMP_CLT_S, FPR32>;
219 defm : PatFPBrcond<SETOLT, FCMP_CLT_S, FPR32>;
236 def : PatStrictFsetccs<SETOLT, FCMP_SLT_S, FPR32>;
259 def : PatFPSelectcc<SETOLT, FCMP_CLT_S, FSEL_xS, FPR32>;
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoZfa.td263 def: PatSetCC<FPR32, strict_fsetcc, SETOLT, FLTQ_S, f32>;
288 def: PatSetCC<FPR64, strict_fsetcc, SETOLT, FLTQ_D, f64>;
318 def: PatSetCC<FPR16, strict_fsetcc, SETOLT, FLTQ_H, f16>;
H A DRISCVInstrInfoD.td416 defm : PatSetCC_m<strict_fsetcc, SETOLT, PseudoQuietFLT_D, Ext>;
436 def : PatSetCC<FPR64, any_fsetccs, SETOLT, FLT_D, f64>;
456 def : PatSetCC<FPR64INX, any_fsetccs, SETOLT, FLT_D_INX, f64>;
476 def : PatSetCC<FPR64IN32X, any_fsetccs, SETOLT, FLT_D_IN32X, f64>;
H A DRISCVInstrInfoZfh.td395 defm : PatSetCC_m<strict_fsetcc, SETOLT, PseudoQuietFLT_H, Ext>;
432 defm : PatSetCC_m<any_fsetccs, SETOLT, FLT_H, Ext>;
H A DRISCVInstrInfoF.td670 defm : PatSetCC_m<strict_fsetcc, SETOLT, PseudoQuietFLT_S, Ext>;
707 defm : PatSetCC_m<any_fsetccs, SETOLT, FLT_S, Ext>;
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfoF2.td380 defm : BRCond_Bin_F2<SETOLT, "f2FCMPLT", BT32, BF32, MVC32>;
402 def : Pat<(brcond (i32 (setcc FPR32Op:$rs1, fpimm0, SETOLT)), bb:$imm16),
404 def : Pat<(i32 (setcc FPR32Op:$rs1, fpimm0, SETOLT)),
406 def : Pat<(select (i32 (setcc FPR32Op:$rs1, fpimm0, SETOLT)), FPR32Op:$rx, FPR32Op:$false),
H A DCSKYInstrInfoF1.td360 defm : BRCond_Bin<SETOLT, "FCMPLT", BT32, BF32, MVC32>;
380 def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETOLT)), bb:$imm16),
382 def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETOLT)),
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DAnalysis.cpp205 case FCmpInst::FCMP_OLT: return ISD::SETOLT; in getFCmpCondCode()
225 case ISD::SETOLT: case ISD::SETULT: return ISD::SETLT; in getFCmpCodeWithoutNaN()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1691 SETOLT, // 0 1 0 0 True if ordered and less than enumerator
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.h110 case ISD::SETOLT: in fpCondCode2Fcc()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrFloat.td87 defm LT : ComparisonFP<SETOLT, "lt ", 0x5d, 0x63>;
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp1678 case ISD::SETOLT: in combineFMinMaxLegacyImpl()
2598 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOLT); in LowerFFLOOR()
2661 SmallestNormal, ISD::SETOLT); in getIsLtSmallestNormal()
2676 Inf, ISD::SETOLT); in getIsFinite()
2695 SmallestNormal, ISD::SETOLT); in getScaledLogInput()
2921 DAG.getSetCC(SL, SetCCVT, Src, RangeCheckConst, ISD::SETOLT); in lowerFEXP2()
2957 SDValue NeedsScaling = DAG.getSetCC(SL, SetCCVT, X, Threshold, ISD::SETOLT); in lowerFEXPUnsafe()
3008 SDValue NeedsScaling = DAG.getSetCC(SL, SetCCVT, X, Threshold, ISD::SETOLT); in lowerFEXP10Unsafe()
3148 DAG.getSetCC(SL, SetCCVT, X, UnderflowCheckConst, ISD::SETOLT); in lowerFEXP()
H A DAMDGPUInstructions.td352 def COND_OLT : PatFrags<(ops), [(OtherVT SETOLT), (OtherVT SETLT)]>;
H A DSIWholeQuadMode.cpp861 case ISD::SETOLT: in lowerKillF32()
H A DR600ISelLowering.cpp86 setCondCodeAction({ISD::SETO, ISD::SETUO, ISD::SETLT, ISD::SETLE, ISD::SETOLT, in R600TargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp526 case ISD::SETOLT: return "setolt"; in getOperationName()
H A DTargetLowering.cpp352 case ISD::SETOLT: in softenSetCCOperands()
5453 case ISD::SETONE: NewCond = IsNegInf ? ISD::SETOGT : ISD::SETOLT; break; in SimplifySetCC()
8735 DAG.getSetCC(DL, CCVT, LHS, RHS, IsMax ? ISD::SETOGT : ISD::SETOLT); in expandFMINIMUM_FMAXIMUM()
8986 ISD::CondCode OrderedOp = IsInvertedFP ? ISD::SETUGE : ISD::SETOLT; in expandIS_FPCLASS()
9005 ISD::CondCode IsFiniteOp = IsInvertedFP ? ISD::SETUGE : ISD::SETOLT; in expandIS_FPCLASS()
9006 ISD::CondCode IsNormalOp = IsInvertedFP ? ISD::SETOLT : ISD::SETUGE; in expandIS_FPCLASS()
12190 isCondCodeLegal(ISD::SETOLT, OpVT))) { in LegalizeSetCCCondCode()
12192 CC2 = ISD::SETOLT; in LegalizeSetCCCondCode()
12201 case ISD::SETOLT: in LegalizeSetCCCondCode()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp4225 case ISD::SETOLT: in SelectCC()
4252 case ISD::SETOLT: in SelectCC()
4300 case ISD::SETOLT: in getPredicateForSetCC()
4327 case ISD::SETOLT: in getCRIdxForSetCC()
4367 case ISD::SETOLT: CC = ISD::SETOGT; Swap = true; break; in getVCmpInst()
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp845 case ISD::SETOLT: in IntCondCCodeToICC()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1790 case ISD::SETOLT: in TranslateM68kCC()
1810 case ISD::SETOLT: // flipped in TranslateM68kCC()
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td911 def SETOLT : CondCode<"FCMP_OLT">;
1578 (setcc node:$lhs, node:$rhs, SETOLT)>;
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaISelLowering.cpp868 case ISD::SETOLT: in getFPBranchKind()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp381 case ISD::SETOLT: in getPTXCmpMode()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp353 setCondCodeAction(ISD::SETOLT, MVT::v64f16, Expand); in initializeHVXLowering()
368 setCondCodeAction(ISD::SETOLT, MVT::v32f32, Expand); in initializeHVXLowering()

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