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Searched refs:SETOLT (Results 1 – 25 of 43) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchFloat32InstrInfo.td189 // SETOLT/SETOLE/SETULT/SETULE/SETLE/SETEQ/SETLT.
192 def : PatFPSetcc<SETOLT, FCMP_CLT_S, FPR32>;
213 defm : PatFPBrcond<SETOLT, FCMP_CLT_S, FPR32>;
230 def : PatStrictFsetccs<SETOLT, FCMP_SLT_S, FPR32>;
253 def : PatFPSelectcc<SETOLT, FCMP_CLT_S, FSEL_xS, FPR32>;
H A DLoongArchFloat64InstrInfo.td169 // SETOLT/SETOLE/SETULT/SETULE/SETLE/SETEQ/SETLT.
172 def : PatFPSetcc<SETOLT, FCMP_CLT_D, FPR64>;
185 defm : PatFPBrcond<SETOLT, FCMP_CLT_D, FPR64>;
199 def : PatStrictFsetccs<SETOLT, FCMP_SLT_D, FPR64>;
218 def : PatFPSelectcc<SETOLT, FCMP_CLT_D, FSEL_xD, FPR64>;
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoZfa.td208 def: PatSetCC<FPR32, strict_fsetcc, SETOLT, FLTQ_S, f32>;
231 def: PatSetCC<FPR64, strict_fsetcc, SETOLT, FLTQ_D, f64>;
259 def: PatSetCC<FPR16, strict_fsetcc, SETOLT, FLTQ_H, f16>;
H A DRISCVInstrInfoD.td405 defm : PatSetCC_m<strict_fsetcc, SETOLT, PseudoQuietFLT_D, Ext>;
425 def : PatSetCC<FPR64, any_fsetccs, SETOLT, FLT_D, f64>;
445 def : PatSetCC<FPR64INX, any_fsetccs, SETOLT, FLT_D_INX, f64>;
465 def : PatSetCC<FPR64IN32X, any_fsetccs, SETOLT, FLT_D_IN32X, f64>;
H A DRISCVInstrInfoZfh.td361 defm : PatSetCC_m<strict_fsetcc, SETOLT, PseudoQuietFLT_H, Ext>;
398 defm : PatSetCC_m<any_fsetccs, SETOLT, FLT_H, Ext>;
H A DRISCVInstrInfoF.td612 defm : PatSetCC_m<strict_fsetcc, SETOLT, PseudoQuietFLT_S, Ext>;
649 defm : PatSetCC_m<any_fsetccs, SETOLT, FLT_S, Ext>;
H A DRISCVInstrInfoVSDPatterns.td1381 defm : VPatFPSetCCSDNode_VV_VF_FV<SETOLT, "PseudoVMFLT", "PseudoVMFGT">;
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfoF2.td380 defm : BRCond_Bin_F2<SETOLT, "f2FCMPLT", BT32, BF32, MVC32>;
402 def : Pat<(brcond (i32 (setcc FPR32Op:$rs1, fpimm0, SETOLT)), bb:$imm16),
404 def : Pat<(i32 (setcc FPR32Op:$rs1, fpimm0, SETOLT)),
406 def : Pat<(select (i32 (setcc FPR32Op:$rs1, fpimm0, SETOLT)), FPR32Op:$rx, FPR32Op:$false),
H A DCSKYInstrInfoF1.td360 defm : BRCond_Bin<SETOLT, "FCMPLT", BT32, BF32, MVC32>;
380 def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETOLT)), bb:$imm16),
382 def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETOLT)),
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DAnalysis.cpp205 case FCmpInst::FCMP_OLT: return ISD::SETOLT; in getFCmpCondCode()
225 case ISD::SETOLT: case ISD::SETULT: return ISD::SETLT; in getFCmpCodeWithoutNaN()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1580 SETOLT, // 0 1 0 0 True if ordered and less than enumerator
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrFloat.td87 defm LT : ComparisonFP<SETOLT, "lt ", 0x5d, 0x63>;
H A DWebAssemblyInstrSIMD.td768 defm LT : SIMDConditionFP<"lt", SETOLT, 67>;
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp1621 case ISD::SETOLT: in combineFMinMaxLegacyImpl()
2541 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOLT); in LowerFFLOOR()
2604 SmallestNormal, ISD::SETOLT); in getIsLtSmallestNormal()
2619 Inf, ISD::SETOLT); in getIsFinite()
2638 SmallestNormal, ISD::SETOLT); in getScaledLogInput()
2864 DAG.getSetCC(SL, SetCCVT, Src, RangeCheckConst, ISD::SETOLT); in lowerFEXP2()
2900 SDValue NeedsScaling = DAG.getSetCC(SL, SetCCVT, X, Threshold, ISD::SETOLT); in lowerFEXPUnsafe()
2950 SDValue NeedsScaling = DAG.getSetCC(SL, SetCCVT, X, Threshold, ISD::SETOLT); in lowerFEXP10Unsafe()
3090 DAG.getSetCC(SL, SetCCVT, X, UnderflowCheckConst, ISD::SETOLT); in lowerFEXP()
H A DAMDGPUInstructions.td352 def COND_OLT : PatFrags<(ops), [(OtherVT SETOLT), (OtherVT SETLT)]>;
H A DSIWholeQuadMode.cpp851 case ISD::SETOLT: in lowerKillF32()
H A DR600ISelLowering.cpp87 setCondCodeAction({ISD::SETO, ISD::SETUO, ISD::SETLT, ISD::SETLE, ISD::SETOLT, in R600TargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp504 case ISD::SETOLT: return "setolt"; in getOperationName()
H A DTargetLowering.cpp338 case ISD::SETOLT: in softenSetCCOperands()
5239 case ISD::SETONE: NewCond = IsNegInf ? ISD::SETOGT : ISD::SETOLT; break; in SimplifySetCC()
11609 TLI.isCondCodeLegal(ISD::SETOLT, OpVT))) { in LegalizeSetCCCondCode()
11611 CC2 = ISD::SETOLT; in LegalizeSetCCCondCode()
11620 case ISD::SETOLT: in LegalizeSetCCCondCode()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp4226 case ISD::SETOLT: in SelectCC()
4253 case ISD::SETOLT: in SelectCC()
4301 case ISD::SETOLT: in getPredicateForSetCC()
4328 case ISD::SETOLT: in getCRIdxForSetCC()
4368 case ISD::SETOLT: CC = ISD::SETOGT; Swap = true; break; in getVCmpInst()
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp856 case ISD::SETOLT: in IntCondCCodeToICC()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1788 case ISD::SETOLT: in TranslateM68kCC()
1808 case ISD::SETOLT: // flipped in TranslateM68kCC()
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td852 def SETOLT : CondCode<"FCMP_OLT">;
1489 (setcc node:$lhs, node:$rhs, SETOLT)>;
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp347 setCondCodeAction(ISD::SETOLT, MVT::v64f16, Expand); in initializeHVXLowering()
360 setCondCodeAction(ISD::SETOLT, MVT::v32f32, Expand); in initializeHVXLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp2595 DAG.getConstantFP(0.5, SL, VT), ISD::SETOLT); in LowerFROUND32()
2621 DAG.getConstantFP(0.5, SL, VT), ISD::SETOLT); in LowerFROUND64()

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